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Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way:e0ea0928d5
("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems:46f9b2c3a2
("drivers: add tzc380 support"). This problem was introduced in commit4ecca33988
("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
208 lines
4.4 KiB
C
208 lines
4.4 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <hisi_ipc.h>
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#include <hisi_sram_map.h>
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static int ipc_init;
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static unsigned int cpu_ipc_num[PLATFORM_CLUSTER_COUNT][PLATFORM_CORE_COUNT_PER_CLUSTER] = {
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{
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HISI_IPC_MCU_INT_SRC_ACPU0_PD,
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HISI_IPC_MCU_INT_SRC_ACPU1_PD,
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HISI_IPC_MCU_INT_SRC_ACPU2_PD,
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HISI_IPC_MCU_INT_SRC_ACPU3_PD,
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},
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{
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HISI_IPC_MCU_INT_SRC_ACPU4_PD,
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HISI_IPC_MCU_INT_SRC_ACPU5_PD,
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HISI_IPC_MCU_INT_SRC_ACPU6_PD,
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HISI_IPC_MCU_INT_SRC_ACPU7_PD,
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}
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};
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int hisi_cpus_pd_in_cluster_besides_curr(unsigned int cpu,
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unsigned int cluster)
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{
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unsigned int val = 0, cpu_val = 0;
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int i;
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val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
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val = val >> (cluster * 16);
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for (i = 0; i < PLATFORM_CORE_COUNT_PER_CLUSTER; i++) {
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if (cpu == i)
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continue;
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cpu_val = (val >> (i * 4)) & 0xF;
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if (cpu_val == 0x8)
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return 0;
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}
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return 1;
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}
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int hisi_cpus_powered_off_besides_curr(unsigned int cpu)
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{
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unsigned int val;
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val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
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return (val == (0x8 << (cpu * 4)));
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}
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static void hisi_ipc_send(unsigned int ipc_num)
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{
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if (!ipc_init) {
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printf("error ipc base is null!!!\n");
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return;
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}
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mmio_write_32(HISI_IPC_CPU_RAW_INT_ADDR, 1 << ipc_num);
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}
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void hisi_ipc_spin_lock(unsigned int signal)
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{
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unsigned int hs_ctrl;
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if (signal >= HISI_IPC_INT_SRC_NUM)
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return;
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do {
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hs_ctrl = mmio_read_32(HISI_IPC_ACPU_CTRL(signal));
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} while (hs_ctrl);
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}
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void hisi_ipc_spin_unlock(unsigned int signal)
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{
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if (signal >= HISI_IPC_INT_SRC_NUM)
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return;
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mmio_write_32(HISI_IPC_ACPU_CTRL(signal), 0);
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}
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void hisi_ipc_cpu_on_off(unsigned int cpu, unsigned int cluster,
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unsigned int mode)
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{
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unsigned int val = 0;
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unsigned int offset;
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if (mode == HISI_IPC_PM_ON)
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offset = cluster * 16 + cpu * 4;
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else
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offset = cluster * 16 + cpu * 4 + 1;
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
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val |= (0x01 << offset);
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mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, val);
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isb();
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dsb();
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
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}
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void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster)
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{
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hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_ON);
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}
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void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster)
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{
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hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_OFF);
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}
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void hisi_ipc_cluster_on_off(unsigned int cpu, unsigned int cluster,
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unsigned int mode)
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{
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unsigned int val = 0;
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unsigned int offset;
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if (mode == HISI_IPC_PM_ON)
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offset = cluster * 4;
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else
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offset = cluster * 4 + 1;
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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val = mmio_read_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR);
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val |= (0x01 << offset);
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mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, val);
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isb();
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dsb();
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
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}
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void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster)
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{
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hisi_ipc_cluster_on_off(cpu, cluster, HISI_IPC_PM_ON);
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}
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void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster)
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{
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hisi_ipc_cluster_on_off(cpu, cluster, HISI_IPC_PM_OFF);
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}
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void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster)
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{
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unsigned int val = 0;
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unsigned int offset;
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offset = cluster * 16 + cpu * 4 + 2;
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
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val |= (0x01 << offset);
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mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, val);
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
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}
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void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster)
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{
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unsigned int val;
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unsigned int offset;
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offset = cluster * 4 + 1;
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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if (hisi_cpus_pd_in_cluster_besides_curr(cpu, cluster)) {
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val = mmio_read_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR);
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val |= (0x01 << offset);
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mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, val);
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}
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
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}
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void hisi_ipc_psci_system_off(void)
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{
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hisi_ipc_send(HISI_IPC_MCU_INT_SRC_ACPU_PD);
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}
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int hisi_ipc_init(void)
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{
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ipc_init = 1;
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mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, 0x8);
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mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, 0x8);
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return 0;
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}
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