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https://github.com/ARM-software/arm-trusted-firmware.git
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234bc7f88e
From now on, platform_def.h must include any header with definitions that are platform-specific (like arm_def.h) and the included headers mustn't include back platform_def.h, and shouldn't be used by other files. Only platform_def.h should be included in other files. This will ensure that all needed definitions are present, rather than needing to include all the headers in all the definitions' headers just in case. This also prevents problems like cyclic dependencies. Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
121 lines
3.6 KiB
ArmAsm
121 lines
3.6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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.weak plat_secondary_cold_boot_setup
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.weak plat_get_my_entrypoint
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.globl css_calc_core_pos_swap_cluster
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.weak plat_is_my_cpu_primary
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/* ---------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup(void);
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*
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* In the normal boot flow, cold-booting secondary CPUs is not yet
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* implemented and they panic.
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*
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* When booting an EL3 payload, secondary CPUs are placed in a holding
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* pen, waiting for their mailbox to be populated. Note that all CPUs
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* share the same mailbox ; therefore, populating it will release all
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* CPUs from their holding pen. If finer-grained control is needed then
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* this should be handled in the code that secondary CPUs jump to.
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* ---------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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#ifndef EL3_PAYLOAD_BASE
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/* TODO: Implement secondary CPU cold boot setup on CSS platforms */
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cb_panic:
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b cb_panic
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#else
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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/* Wait until the mailbox gets populated */
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poll_mailbox:
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ldr x1, [x0]
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cbz x1, 1f
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br x1
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1:
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wfe
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b poll_mailbox
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#endif /* EL3_PAYLOAD_BASE */
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot. On CSS platforms, this distinction is based on the contents of
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* the Trusted Mailbox. It is initialised to zero by the SCP before the
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* AP cores are released from reset. Therefore, a zero mailbox means
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* it's a cold reset.
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*
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* This functions returns the contents of the mailbox, i.e.:
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* - 0 for a cold boot;
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* - the warm boot entrypoint for a warm boot.
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------------
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* unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr)
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* Utility function to calculate the core position by
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* swapping the cluster order. This is necessary in order to
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* match the format of the boot information passed by the SCP
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* and read in plat_is_my_cpu_primary below.
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* -----------------------------------------------------------
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*/
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func css_calc_core_pos_swap_cluster
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
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add x0, x1, x0, LSR #6
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ret
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endfunc css_calc_core_pos_swap_cluster
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu (applicable ony after a cold boot)
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* -----------------------------------------------------
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*/
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#if CSS_USE_SCMI_SDS_DRIVER
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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mov x4, x0
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bl sds_get_primary_cpu_id
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/* Check for error */
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mov x1, #0xffffffff
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cmp x0, x1
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b.eq 1f
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cmp x0, x4
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cset w0, eq
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ret x9
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1:
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no_ret plat_panic_handler
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endfunc plat_is_my_cpu_primary
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#else
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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mov_imm x1, SCP_BOOT_CFG_ADDR
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ldr x1, [x1]
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ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
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#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
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cmp x0, x1
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cset w0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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#endif
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