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https://github.com/ARM-software/arm-trusted-firmware.git
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f97b579502
A TZC400 controller is placed inline on DRAM channels and regulates the secure and non-secure accesses to both secure and non-secure regions of the DRAM memory. Configure each of the TZC controllers across the Chips. For use by secure software, configure the first chip's trustzone controller to protect the upper 16MB of the memory of the first DRAM block for secure accesses only. The other regions are configured for non-secure read write access. For all the remote chips, all the DRAM regions are allowed for non-secure read and write access. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
65 lines
1.4 KiB
C
65 lines
1.4 KiB
C
/*
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* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <plat/arm/common/plat_arm.h>
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#include <platform_def.h>
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/* TZC memory regions for the first chip */
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static const arm_tzc_regions_info_t tzc_regions[] = {
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ARM_TZC_REGIONS_DEF,
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{}
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};
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#if CSS_SGI_CHIP_COUNT > 1
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static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
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{
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/* TZC memory regions for second chip */
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SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
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{}
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},
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#if CSS_SGI_CHIP_COUNT > 2
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{
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/* TZC memory regions for third chip */
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SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
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{}
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},
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#endif
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#if CSS_SGI_CHIP_COUNT > 3
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{
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/* TZC memory regions for fourth chip */
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SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
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{}
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},
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#endif
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};
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#endif /* CSS_SGI_CHIP_COUNT */
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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unsigned int i;
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INFO("Configuring TrustZone Controller for Chip 0\n");
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for (i = 0; i < TZC400_COUNT; i++) {
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arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
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}
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#if CSS_SGI_CHIP_COUNT > 1
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unsigned int j;
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for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
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INFO("Configuring TrustZone Controller for Chip %u\n", i);
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for (j = 0; j < TZC400_COUNT; j++) {
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arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
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+ TZC400_BASE(j), tzc_regions_mc[i-1]);
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}
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}
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#endif
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}
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