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1d74b4bbba
The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different across all the Neoverse reference design platforms. This value depends on the number of address bits used per chip. So let all platforms define CSS_SGI_ADDR_BITS_PER_CHIP which specifies the number of address bits used per chip. In addition to this, reuse the definition of CSS_SGI_ADDR_BITS_PER_CHIP for single chip platforms and CSS_SGI_REMOTE_CHIP_MEM_OFFSET for multi- chip platforms to determine the maximum address space size. Also, increase the RD-N2 multi-chip address space per chip from 4TB to 64TB. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: If5e69ec26c2389304c71911729d4addbdf8b2686
69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_soc_platform_def.h>
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#define PLAT_ARM_CLUSTER_COUNT U(16)
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
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#define CSS_SGI_MAX_PE_PER_CPU U(1)
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/* TZC Related Constants */
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#define PLAT_ARM_TZC_BASE UL(0x21830000)
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
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#define TZC400_OFFSET UL(0x1000000)
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#define TZC400_COUNT 4
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#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
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(n * TZC400_OFFSET))
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#define TZC_NSAID_ALL_AP U(0)
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#define TZC_NSAID_PCI U(1)
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#define TZC_NSAID_HDLCD0 U(2)
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#define TZC_NSAID_CLCD U(7)
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#define TZC_NSAID_AP U(9)
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#define TZC_NSAID_VIRTIO U(15)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
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/* Maximum number of address bits used per chip */
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#define CSS_SGI_ADDR_BITS_PER_CHIP U(42)
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x30140000)
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#endif /* PLATFORM_DEF_H */
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