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https://github.com/ARM-software/arm-trusted-firmware.git
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05330a49cd
The EL3 runtime firmware has been running from internal trusted SRAM space on the Morello platform. Due to unavailability of tag support for the internal trusted SRAM this becomes a problem if we enable capability pointers in BL31. To support capability pointers in BL31 it has to be run from the main DDR memory space. This patch updates the Morello platform configuration such that BL31 is loaded and run from DDR space. Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Change-Id: I16d4d757fb6f58c364f5133236d50fc06845e0b4
111 lines
3.5 KiB
Makefile
111 lines
3.5 KiB
Makefile
#
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# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Making sure the Morello platform type is specified
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ifeq ($(filter ${TARGET_PLATFORM}, fvp soc),)
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$(error TARGET_PLATFORM must be fvp or soc)
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endif
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MORELLO_BASE := plat/arm/board/morello
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INTERCONNECT_SOURCES := ${MORELLO_BASE}/morello_interconnect.c
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PLAT_INCLUDES := -I${MORELLO_BASE}/include
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MORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S
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# GIC-600 configuration
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GICV3_SUPPORT_GIC600 := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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MORELLO_GIC_SOURCES := ${GICV3_SOURCES} \
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plat/common/plat_gicv3.c \
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plat/arm/common/arm_gicv3.c \
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PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \
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${MORELLO_BASE}/aarch64/morello_helper.S
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BL1_SOURCES := ${MORELLO_CPU_SOURCES} \
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${INTERCONNECT_SOURCES} \
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${MORELLO_BASE}/morello_err.c \
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${MORELLO_BASE}/morello_trusted_boot.c \
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${MORELLO_BASE}/morello_bl1_setup.c \
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drivers/arm/sbsa/sbsa.c
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BL2_SOURCES := ${MORELLO_BASE}/morello_security.c \
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${MORELLO_BASE}/morello_err.c \
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${MORELLO_BASE}/morello_trusted_boot.c \
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${MORELLO_BASE}/morello_bl2_setup.c \
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${MORELLO_BASE}/morello_image_load.c \
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lib/utils/mem_region.c \
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drivers/arm/css/sds/sds.c
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BL31_SOURCES := ${MORELLO_CPU_SOURCES} \
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${INTERCONNECT_SOURCES} \
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${MORELLO_GIC_SOURCES} \
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${MORELLO_BASE}/morello_bl31_setup.c \
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${MORELLO_BASE}/morello_topology.c \
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${MORELLO_BASE}/morello_security.c \
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drivers/arm/css/sds/sds.c
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FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts \
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${MORELLO_BASE}/fdts/morello_fw_config.dts \
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${MORELLO_BASE}/fdts/morello_tb_fw_config.dts \
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${MORELLO_BASE}/fdts/morello_nt_fw_config.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/morello_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_tb_fw_config.dtb
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_nt_fw_config.dtb
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
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MORELLO_FW_NVCTR_VAL := 0
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TFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL}
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NTFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL}
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# TF-A not required to load the SCP Images
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override CSS_LOAD_SCP_IMAGES := 0
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override NEED_BL2U := no
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# 32 bit mode not supported
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override CTX_INCLUDE_AARCH32_REGS := 0
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override ARM_PLAT_MT := 1
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override ARM_BL31_IN_DRAM := 1
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# Errata workarounds:
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ERRATA_N1_1868343 := 1
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# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
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# SCP during power management operations and for SCP RAM Firmware transfer.
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CSS_USE_SCMI_SDS_DRIVER := 1
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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# When building for systems with hardware-assisted coherency, there's no need to
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# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
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USE_COHERENT_MEM := 0
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# Add TARGET_PLATFORM to differentiate between Morello FVP and Morello SoC platform
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$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
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# Add MORELLO_FW_NVCTR_VAL
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$(eval $(call add_define,MORELLO_FW_NVCTR_VAL))
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include plat/arm/common/arm_common.mk
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include plat/arm/css/common/css_common.mk
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include plat/arm/board/common/board_common.mk
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