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https://github.com/ARM-software/arm-trusted-firmware.git
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234bc7f88e
From now on, platform_def.h must include any header with definitions that are platform-specific (like arm_def.h) and the included headers mustn't include back platform_def.h, and shouldn't be used by other files. Only platform_def.h should be included in other files. This will ensure that all needed definitions are present, rather than needing to include all the headers in all the definitions' headers just in case. This also prevents problems like cyclic dependencies. Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
84 lines
3.2 KiB
C
84 lines
3.2 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef JUNO_TZMP1_DEF_H
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#define JUNO_TZMP1_DEF_H
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/*
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* Public memory regions for both protected and non-protected mode
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*
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* OPTEE shared memory 0xFEE00000 - 0xFEFFFFFF
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*/
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#define JUNO_AP_TZC_SHARE_DRAM1_SIZE ULL(0x02000000)
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#define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
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JUNO_AP_TZC_SHARE_DRAM1_SIZE)
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#define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1)
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/* ARM_MEDIA_FEATURES for MEDIA GPU Protect Mode Test */
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#define JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE 8 /* GPU/DPU protected, VPU outbuf */
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#define JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED 7 /* VPU protected */
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#define JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE 10 /* VPU private (firmware) */
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#define JUNO_VPU_TZC_PRIV_DRAM1_SIZE ULL(0x02000000)
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#define JUNO_VPU_TZC_PRIV_DRAM1_BASE (JUNO_AP_TZC_SHARE_DRAM1_BASE - \
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JUNO_VPU_TZC_PRIV_DRAM1_SIZE)
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#define JUNO_VPU_TZC_PRIV_DRAM1_END (JUNO_AP_TZC_SHARE_DRAM1_BASE - 1)
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/* Video input protected buffer follows upper item */
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#define JUNO_VPU_TZC_PROT_DRAM1_SIZE ULL(0x06000000)
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#define JUNO_VPU_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PRIV_DRAM1_BASE - \
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JUNO_VPU_TZC_PROT_DRAM1_SIZE)
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#define JUNO_VPU_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PRIV_DRAM1_BASE - 1)
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/* Video, graphics and display shares same NSAID and same protected buffer */
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#define JUNO_MEDIA_TZC_PROT_DRAM1_SIZE ULL(0x0e000000)
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#define JUNO_MEDIA_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PROT_DRAM1_BASE - \
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JUNO_MEDIA_TZC_PROT_DRAM1_SIZE)
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#define JUNO_MEDIA_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PROT_DRAM1_BASE - 1)
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/* Rest of DRAM1 are Non-Secure public buffer */
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#define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE
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#define JUNO_NS_DRAM1_PT1_END (JUNO_MEDIA_TZC_PROT_DRAM1_BASE - 1)
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#define JUNO_NS_DRAM1_PT1_SIZE (JUNO_NS_DRAM1_PT1_END - \
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JUNO_NS_DRAM1_PT1_BASE + 1)
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/* TZC filter flags */
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#define JUNO_MEDIA_TZC_NS_DEV_ACCESS (PLAT_ARM_TZC_NS_DEV_ACCESS | \
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TZC_REGION_ACCESS_RD(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE))
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/* VPU / GPU /DPU protected access */
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#define JUNO_MEDIA_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \
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TZC_REGION_ACCESS_WR(TZC400_NSAID_AP))
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#define JUNO_VPU_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED))
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#define JUNO_VPU_TZC_PRIV_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE))
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/*******************************************************************************
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* Mali-DP650 related constants
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******************************************************************************/
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/* Base address of DP650 */
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#define DP650_BASE 0x6f200000
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/* offset to PROT_NSAID register */
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#define DP650_PROT_NSAID_OFFSET 0x10004
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/* config to PROT_NSAID register */
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#define DP650_PROT_NSAID_CONFIG 0x08008888
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/*******************************************************************************
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* Mali-V550 related constants
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******************************************************************************/
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/* Base address of V550 */
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#define V550_BASE 0x6f030000
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/* offset to PROTCTRL register */
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#define V550_PROTCTRL_OFFSET 0x0040
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/* config to PROTCTRL register */
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#define V550_PROTCTRL_CONFIG 0xa8700000
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#endif /* JUNO_TZMP1_DEF_H */
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