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6138ffbc12
The motivation behind this patch and following patches is to extract information about the platform in runtime rather than depending on compile time macros such as FVP_CLUSTER_COUNT. This partially enables us to use a single binary for a family of platforms which all have similar hardware capabilities but differ in configurations. we populate the data structure describing the power domain hierarchy of the platform dynamically by querying the number of clusters and cpus using fconf getter APIs. Compile time macro such as FVP_CLUSTER_COUNT is still needed as it determines the size of related data structures. Note that the cpu-map node in HW_CONFIG dts represents a logical hierarchy of power domains of CPU. However, in reality, the power domains may not have been physically built in such hierarchy. Change-Id: Ibcbb5ca7b2c969f8ad03ab2eab289725245af7a9 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
124 lines
4.2 KiB
C
124 lines
4.2 KiB
C
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch.h>
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#include <drivers/arm/fvp/fvp_pwrc.h>
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#include <fconf_hw_config_getter.h>
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#include <lib/cassert.h>
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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/* The FVP power domain tree descriptor */
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static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
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CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)),
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assert_invalid_fvp_cluster_count);
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/*******************************************************************************
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* This function dynamically constructs the topology according to cpu-map node
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* in HW_CONFIG dtb and returns it.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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unsigned int i;
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uint32_t cluster_count, cpus_per_cluster;
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/*
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* fconf APIs are not supported for RESET_TO_SP_MIN, RESET_TO_BL31 and
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* BL2_AT_EL3 systems.
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*/
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#if RESET_TO_SP_MIN || RESET_TO_BL31 || BL2_AT_EL3
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cluster_count = FVP_CLUSTER_COUNT;
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cpus_per_cluster = FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU;
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#else
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cluster_count = FCONF_GET_PROPERTY(hw_config, topology, plat_cluster_count);
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cpus_per_cluster = FCONF_GET_PROPERTY(hw_config, topology, cluster_cpu_count);
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/* Several FVP Models use the same blanket dts. Ex: FVP_Base_Cortex-A65x4
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* and FVP_Base_Cortex-A65AEx8 both use same dts but have different number of
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* CPUs in the cluster, as reflected by build flags FVP_MAX_CPUS_PER_CLUSTER.
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* Take the minimum of two to ensure PSCI functions do not exceed the size of
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* the PSCI data structures allocated at build time.
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*/
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cpus_per_cluster = MIN(cpus_per_cluster,
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(uint32_t)(FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU));
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#endif
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assert(cluster_count > 0U);
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assert(cpus_per_cluster > 0U);
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/*
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* The highest level is the system level. The next level is constituted
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* by clusters and then cores in clusters.
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*/
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fvp_power_domain_tree_desc[0] = 1;
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fvp_power_domain_tree_desc[1] = (unsigned char)cluster_count;
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for (i = 0; i < cluster_count; i++)
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fvp_power_domain_tree_desc[i + 2] = (unsigned char)cpus_per_cluster;
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return fvp_power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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******************************************************************************/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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{
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return FVP_MAX_CPUS_PER_CLUSTER;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int clus_id, cpu_id, thread_id;
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/* Validate affinity fields */
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if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) {
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thread_id = MPIDR_AFFLVL0_VAL(mpidr);
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cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
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clus_id = MPIDR_AFFLVL2_VAL(mpidr);
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} else {
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thread_id = 0;
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cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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clus_id = MPIDR_AFFLVL1_VAL(mpidr);
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}
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if (clus_id >= FVP_CLUSTER_COUNT)
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return -1;
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if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER)
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return -1;
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if (thread_id >= FVP_MAX_PE_PER_CPU)
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return -1;
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if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID)
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return -1;
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/*
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* Core position calculation for FVP platform depends on the MT bit in
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* MPIDR. This function cannot assume that the supplied MPIDR has the MT
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* bit set even if the implementation has. For example, PSCI clients
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* might supply MPIDR values without the MT bit set. Therefore, we
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* inject the current PE's MT bit so as to get the calculation correct.
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* This of course assumes that none or all CPUs on the platform has MT
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* bit set.
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*/
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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return (int) plat_arm_calc_core_pos(mpidr);
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}
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