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https://github.com/ARM-software/arm-trusted-firmware.git
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e80354212f
Currently only the lowest 2 DRAM region were configured in the TrustZone Controller, but the platform supports 6 regions spanning the whole address space. Configuring all of them to allow tests to access memory also in those higher memory regions. FVP memory map: https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map Note that last row is wrong, describing a non-existing 56bit address, all region labels should be shifted upward. Issue has been reported and next release will be correct. Change-Id: I695fe8e24aff67d75e74635ba32a133342289eb4 Signed-off-by: Federico Recanati <federico.recanati@arm.com>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/plat_arm.h>
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#include <platform_def.h>
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/*
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* We assume that all security programming is done by the primary core.
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*/
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void plat_arm_security_setup(void)
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{
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/*
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* The Base FVP has a TrustZone address space controller, the Foundation
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* FVP does not. Trying to program the device on the foundation FVP will
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* cause an abort.
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*
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* If the platform had additional peripheral specific security
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* configurations, those would be configured here.
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*/
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const arm_tzc_regions_info_t fvp_tzc_regions[] = {
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ARM_TZC_REGIONS_DEF,
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#if !SPM_MM && !ENABLE_RME
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{FVP_DRAM3_BASE, FVP_DRAM3_END,
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
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{FVP_DRAM4_BASE, FVP_DRAM4_END,
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
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{FVP_DRAM5_BASE, FVP_DRAM5_END,
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
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{FVP_DRAM6_BASE, FVP_DRAM6_END,
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ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
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#endif
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{0}
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};
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if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
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arm_tzc400_setup(PLAT_ARM_TZC_BASE, fvp_tzc_regions);
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}
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