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https://github.com/ARM-software/arm-trusted-firmware.git
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e2b18771fc
When using SCPI as the PSCI backend, firmware can wake up the CPUs and cluster from sleep, so CPU idle states are available for the rich OS to use. In that case, advertise them to the rich OS via the DTB. Change-Id: I718ef6ef41212fe5213b11b4799613adbbe6e0eb Signed-off-by: Samuel Holland <samuel@sholland.org>
61 lines
1.2 KiB
C
61 lines
1.2 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <common/fdt_fixup.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_private.h>
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static bool psci_is_scpi;
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#if SUNXI_PSCI_USE_SCPI
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bool sunxi_psci_is_scpi(void)
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{
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return psci_is_scpi;
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}
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#endif
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int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entry point must be in DRAM */
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if (ns_entrypoint < SUNXI_DRAM_BASE) {
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return PSCI_E_INVALID_ADDRESS;
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}
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return PSCI_E_SUCCESS;
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}
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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assert(psci_ops);
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/* Program all CPU entry points. */
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for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
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mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
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sec_entrypoint & 0xffffffff);
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mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
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sec_entrypoint >> 32);
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}
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if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {
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INFO("PSCI: Suspend is available via SCPI\n");
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psci_is_scpi = true;
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} else {
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INFO("PSCI: Suspend is unavailable\n");
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sunxi_set_native_psci_ops(psci_ops);
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}
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return 0;
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}
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