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https://github.com/ARM-software/arm-trusted-firmware.git
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159c36fd2f
Aligning the PSCI and SCPI power states avoids some code to translate between the two. This also makes room for an intermediate power state, for future firmware capability growth. Change-Id: I26691085f277a96bd405e3305ab0fe390a92b418 Signed-off-by: Samuel Holland <samuel@sholland.org>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include <sunxi_mmap.h>
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#ifdef SUNXI_BL31_IN_DRAM
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#define BL31_BASE SUNXI_DRAM_BASE
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#define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000)
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#define MAX_XLAT_TABLES 4
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE
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#else /* !SUNXI_BL31_IN_DRAM */
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#define BL31_BASE (SUNXI_SRAM_A2_BASE + \
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SUNXI_SRAM_A2_BL31_OFFSET)
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#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \
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SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
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/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
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#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
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#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
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#define MAX_XLAT_TABLES 1
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
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#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE
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/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
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#define SUNXI_SCP_BASE BL31_LIMIT
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#define SUNXI_SCP_SIZE 0x4000
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#endif /* SUNXI_BL31_IN_DRAM */
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/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
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#define SUNXI_DRAM_MAP_SIZE (64U << 20)
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define MAX_STATIC_MMAP_REGIONS 3
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#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
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(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
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/* These states are used directly for SCPI communication. */
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#define PLAT_MAX_PWR_LVL_STATES U(3)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(3)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_NUM_PWR_DOMAINS (U(1) + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
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#ifndef SPD_none
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#ifndef BL32_BASE
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#define BL32_BASE SUNXI_DRAM_BASE
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#endif
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#endif
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#endif /* PLATFORM_DEF_H */
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