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12af5ed4fb
Previously the errata reporting was optional for CPU operation files and this was achieved by making use of weak reference to resolve to 0 if the symbol is not defined. This is error prone when adding new CPU operation files and weak references are problematic when fixing up dynamic relocations. Hence this patch removes the weak reference and makes it mandatory for the CPU operation files to define the errata reporting function. Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
133 lines
3.3 KiB
ArmAsm
133 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a32.h>
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#include <cpu_macros.S>
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* Clobbers: r0-r1
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* ---------------------------------------------
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*/
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func cortex_a32_disable_smp
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ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
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stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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isb
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dsb sy
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bx lr
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endfunc cortex_a32_disable_smp
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A32.
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* Clobbers: r0-r1
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* -------------------------------------------------
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*/
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func cortex_a32_reset_func
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
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stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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isb
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bx lr
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endfunc cortex_a32_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A32.
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* Clobbers: r0-r3
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* ----------------------------------------------------
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*/
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func cortex_a32_core_pwr_dwn
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a32_disable_smp
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endfunc cortex_a32_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A32.
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* Clobbers: r0-r3
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* -------------------------------------------------------
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*/
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func cortex_a32_cluster_pwr_dwn
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 cache.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 cache.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a32_disable_smp
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endfunc cortex_a32_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A32. Must follow AAPCS.
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*/
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func cortex_a32_errata_report
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bx lr
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endfunc cortex_a32_errata_report
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#endif
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declare_cpu_ops cortex_a32, CORTEX_A32_MIDR, \
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cortex_a32_reset_func, \
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cortex_a32_core_pwr_dwn, \
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cortex_a32_cluster_pwr_dwn
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