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https://github.com/ARM-software/arm-trusted-firmware.git
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a28471722a
This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
40 lines
1.2 KiB
ArmAsm
40 lines
1.2 KiB
ArmAsm
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef CCI_MACROS_S
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#define CCI_MACROS_S
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#include <drivers/arm/cci.h>
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#include <platform_def.h>
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ------------------------------------------------
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* The below required platform porting macro prints
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* out relevant interconnect registers whenever an
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* unhandled exception is taken in BL31.
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* Clobbers: x0 - x9, sp
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* ------------------------------------------------
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*/
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.macro print_cci_regs
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adr x6, cci_iface_regs
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/* Store in x7 the base address of the first interface */
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mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
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PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX))
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ldr w8, [x7, #SNOOP_CTRL_REG]
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/* Store in x7 the base address of the second interface */
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mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
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PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX))
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ldr w9, [x7, #SNOOP_CTRL_REG]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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.endm
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#endif /* CCI_MACROS_S */
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