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5a91c439cb
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal clock can also run at 40 MHz (this is board specific). The frequency of the xtal clock is determined by a value on a strapping pin during SOC reset. The code to determine this frequency is already in A3K's comphy driver. Move the get_ref_clk() function from the comphy driver to a separate file and use it for UART parent clock rate determination. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
106 lines
2.7 KiB
C
106 lines
2.7 KiB
C
/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef PLAT_MARVELL_H
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#define PLAT_MARVELL_H
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#include <stdint.h>
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#include <common/bl_common.h>
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#include <lib/cassert.h>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/*
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* Extern declarations common to Marvell standard platforms
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*/
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extern const mmap_region_t plat_marvell_mmap[];
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#define MARVELL_CASSERT_MMAP \
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CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \
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<= MAX_MMAP_REGIONS, \
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assert_max_mmap_regions)
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/*
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* Utility functions common to Marvell standard platforms
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*/
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void marvell_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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, uintptr_t coh_start,
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uintptr_t coh_limit
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#endif
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);
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/* Console utility functions */
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void marvell_console_boot_init(void);
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void marvell_console_boot_end(void);
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void marvell_console_runtime_init(void);
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void marvell_console_runtime_end(void);
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/* IO storage utility functions */
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void marvell_io_setup(void);
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/* Systimer utility function */
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void marvell_configure_sys_timer(void);
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/* Topology utility function */
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int marvell_check_mpidr(u_register_t mpidr);
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/* BL1 utility functions */
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void marvell_bl1_early_platform_setup(void);
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void marvell_bl1_platform_setup(void);
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void marvell_bl1_plat_arch_setup(void);
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/* BL2 utility functions */
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void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
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void marvell_bl2_platform_setup(void);
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void marvell_bl2_plat_arch_setup(void);
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uint32_t marvell_get_spsr_for_bl32_entry(void);
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uint32_t marvell_get_spsr_for_bl33_entry(void);
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/* BL31 utility functions */
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void marvell_bl31_early_platform_setup(void *from_bl2,
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uintptr_t soc_fw_config,
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uintptr_t hw_config,
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void *plat_params_from_bl2);
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void marvell_bl31_platform_setup(void);
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void marvell_bl31_plat_runtime_setup(void);
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void marvell_bl31_plat_arch_setup(void);
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/* FIP TOC validity check */
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int marvell_io_is_toc_valid(void);
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/*
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* PSCI functionality
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*/
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void marvell_psci_arch_init(int idx);
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void plat_marvell_system_reset(void);
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/*
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* Optional functions required in Marvell standard platforms
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*/
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void plat_marvell_io_setup(void);
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int plat_marvell_get_alt_image_source(
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unsigned int image_id,
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uintptr_t *dev_handle,
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uintptr_t *image_spec);
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unsigned int plat_marvell_calc_core_pos(u_register_t mpidr);
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void plat_marvell_interconnect_init(void);
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void plat_marvell_interconnect_enter_coherency(void);
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const mmap_region_t *plat_marvell_get_mmap(void);
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uint32_t get_ref_clk(void);
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#endif /* PLAT_MARVELL_H */
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