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cedfa04ba5
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the size of translation tables by increasing the maximum permitted value of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and VSTCR_EL2. This feature is supported in AArch64 state only. This patch adds support for this feature to both versions of the translation tables library. It also removes the static build time checks for virtual address space size checks to runtime assertions. Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
73 lines
2.4 KiB
C
73 lines
2.4 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef XLAT_TABLES_AARCH32_H
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#define XLAT_TABLES_AARCH32_H
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#include <arch.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#if !defined(PAGE_SIZE)
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#error "PAGE_SIZE is not defined."
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#endif
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/*
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* In AArch32 state, the MMU only supports 4KB page granularity, which means
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* that the first translation table level is either 1 or 2. Both of them are
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* allowed to have block and table descriptors. See section G4.5.6 of the
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* ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information.
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*
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* The define below specifies the first table level that allows block
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* descriptors.
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*/
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#if PAGE_SIZE != PAGE_SIZE_4KB
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#error "Invalid granule size. AArch32 supports 4KB pages only."
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#endif
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#define MIN_LVL_BLOCK_DESC U(1)
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#define XLAT_TABLE_LEVEL_MIN U(1)
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/*
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* Define the architectural limits of the virtual address space in AArch32
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* state.
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*
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* TTBCR.TxSZ is calculated as 32 minus the width of said address space. The
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* value of TTBCR.TxSZ must be in the range 0 to 7 [1], which means that the
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* virtual address space width must be in the range 32 to 25 bits.
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*
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* [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information, Section G4.6.5
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*/
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#define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(32) - TTBCR_TxSZ_MAX))
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#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(32) - TTBCR_TxSZ_MIN))
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/*
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* Here we calculate the initial lookup level from the value of the given
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* virtual address space size. For a 4 KB page size,
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* - level 1 supports virtual address spaces of widths 32 to 31 bits;
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* - level 2 from 30 to 25.
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*
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* Wider or narrower address spaces are not supported. As a result, level 3
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* cannot be used as the initial lookup level with 4 KB granularity.
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information, Section G4.6.5
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*
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* For example, for a 31-bit address space (i.e. virt_addr_space_size ==
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* 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table
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* G4-5 in the ARM ARM, the initial lookup level for an address space like that
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* is 1.
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*
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* Note that this macro assumes that the given virtual address space size is
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* valid.
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*/
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#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_sz) \
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(((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? \
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U(1) : U(2))
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#endif /* XLAT_TABLES_AARCH32_H */
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