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c4187c9c4b
Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_E1_H
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#define NEOVERSE_E1_H
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#include <lib/utils_def.h>
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#define NEOVERSE_E1_MIDR U(0x410FD4A0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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#endif /* NEOVERSE_E1_H */
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