Maninder Singh 00bb8c37e0 fix(nxp-ddr): apply Max CDD values for warm boot ...

Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466

2022-11-22 16:35:19 +08:00

..

csr.h

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30

ddr4fw.h

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30

ddrphy.mk

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30

input.h

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30

messages.h

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30

phy.c

fix(nxp-ddr): apply Max CDD values for warm boot

2022-11-22 16:35:19 +08:00

phy.h

fix(nxp-ddr): apply Max CDD values for warm boot

2022-11-22 16:35:19 +08:00

pie.h

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30