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Under certain configurations of PPS and L0GPTSZ a macro could result in a right shift by 64 bits. This patch removes that possibility by limiting the total size of each shift to the maximum width of the L0 or L1 index field in a physical address. In addition, it adds more detail about how these values are calculated. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie71c8e6f922a5bb522a6169701bfc36fc99f765a