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6ca2046ef1
To use power manager function more easier, we add some drivers to let the implementation easier. Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Change-Id: Ibc6e1680c4534592ed37de49da39b6667f468ea1
215 lines
6.7 KiB
C
215 lines
6.7 KiB
C
/*
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* Copyright (c) 2022, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTK_PM_H
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#define MTK_PM_H
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#include <lib/psci/psci.h>
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#if MTK_PUBEVENT_ENABLE
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#include <mtk_event/mtk_pubsub_events.h>
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#endif
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#define MTK_CPUPM_E_OK (0)
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#define MTK_CPUPM_E_UNKNOWN (-1)
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#define MTK_CPUPM_E_ERR (-2)
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#define MTK_CPUPM_E_FAIL (-3)
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#define MTK_CPUPM_E_NOT_SUPPORT (-4)
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#define MTK_CPUPM_FN_PWR_LOCK_AQUIRE BIT(0)
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#define MTK_CPUPM_FN_INIT BIT(1)
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#define MTK_CPUPM_FN_PWR_STATE_VALID BIT(2)
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#define MTK_CPUPM_FN_PWR_ON_CORE_PREPARE BIT(3)
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#define MTK_CPUPM_FN_SUSPEND_CORE BIT(4)
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#define MTK_CPUPM_FN_RESUME_CORE BIT(5)
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#define MTK_CPUPM_FN_SUSPEND_CLUSTER BIT(6)
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#define MTK_CPUPM_FN_RESUME_CLUSTER BIT(7)
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#define MTK_CPUPM_FN_SUSPEND_MCUSYS BIT(8)
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#define MTK_CPUPM_FN_RESUME_MCUSYS BIT(9)
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#define MTK_CPUPM_FN_CPUPM_GET_PWR_STATE BIT(10)
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#define MTK_CPUPM_FN_SMP_INIT BIT(11)
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#define MTK_CPUPM_FN_SMP_CORE_ON BIT(12)
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#define MTK_CPUPM_FN_SMP_CORE_OFF BIT(13)
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enum mtk_cpupm_pstate {
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MTK_CPUPM_CORE_ON,
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MTK_CPUPM_CORE_OFF,
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MTK_CPUPM_CORE_SUSPEND,
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MTK_CPUPM_CORE_RESUME,
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MTK_CPUPM_CLUSTER_SUSPEND,
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MTK_CPUPM_CLUSTER_RESUME,
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MTK_CPUPM_MCUSYS_SUSPEND,
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MTK_CPUPM_MCUSYS_RESUME,
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};
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enum mtk_cpu_pm_mode {
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MTK_CPU_PM_CPUIDLE,
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MTK_CPU_PM_SMP,
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};
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#define MT_IRQ_REMAIN_MAX (32)
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#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
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struct mt_irqremain {
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unsigned int count;
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unsigned int irqs[MT_IRQ_REMAIN_MAX];
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unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
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unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
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};
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typedef void (*plat_init_func)(unsigned int, uintptr_t);
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struct plat_pm_smp_ctrl {
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plat_init_func init;
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int (*pwr_domain_on)(u_register_t mpidr);
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void (*pwr_domain_off)(const psci_power_state_t *target_state);
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void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
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};
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struct plat_pm_pwr_ctrl {
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void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
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void (*pwr_domain_on_finish_late)(const psci_power_state_t *target_state);
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void (*pwr_domain_suspend_finish)(const psci_power_state_t *target_state);
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int (*validate_power_state)(unsigned int power_state, psci_power_state_t *req_state);
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void (*get_sys_suspend_power_state)(psci_power_state_t *req_state);
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};
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struct plat_pm_reset_ctrl {
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__dead2 void (*system_off)();
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__dead2 void (*system_reset)();
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int (*system_reset2)(int is_vendor, int reset_type, u_register_t cookie);
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};
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struct mtk_cpu_pm_info {
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unsigned int cpuid;
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unsigned int mode;
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};
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struct mtk_cpu_pm_state {
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unsigned int afflv;
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unsigned int state_id;
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const psci_power_state_t *raw;
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};
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struct mtk_cpupm_pwrstate {
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struct mtk_cpu_pm_info info;
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struct mtk_cpu_pm_state pwr;
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};
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struct mtk_cpu_smp_ops {
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void (*init)(unsigned int cpu, uintptr_t sec_entrypoint);
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int (*cpu_pwr_on_prepare)(unsigned int cpu, uintptr_t entry);
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void (*cpu_on)(const struct mtk_cpupm_pwrstate *state);
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void (*cpu_off)(const struct mtk_cpupm_pwrstate *state);
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int (*invoke)(unsigned int funcID, void *priv);
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};
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#define MT_CPUPM_PWR_DOMAIN_CORE BIT(0)
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#define MT_CPUPM_PWR_DOMAIN_PERCORE_DSU BIT(1)
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#define MT_CPUPM_PWR_DOMAIN_PERCORE_DSU_MEM BIT(2)
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#define MT_CPUPM_PWR_DOMAIN_CLUSTER BIT(3)
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#define MT_CPUPM_PWR_DOMAIN_MCUSYS BIT(4)
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#define MT_CPUPM_PWR_DOMAIN_SUSPEND BIT(5)
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enum mt_cpupm_pwr_domain {
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CPUPM_PWR_ON,
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CPUPM_PWR_OFF,
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};
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typedef unsigned int mtk_pstate_type;
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struct mtk_cpu_pm_ops {
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void (*init)(unsigned int cpu, uintptr_t sec_entrypoint);
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unsigned int (*get_pstate)(enum mt_cpupm_pwr_domain domain,
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const mtk_pstate_type psci_state,
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const struct mtk_cpupm_pwrstate *state);
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int (*pwr_state_valid)(unsigned int afflv, unsigned int state);
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void (*cpu_suspend)(const struct mtk_cpupm_pwrstate *state);
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void (*cpu_resume)(const struct mtk_cpupm_pwrstate *state);
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void (*cluster_suspend)(const struct mtk_cpupm_pwrstate *state);
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void (*cluster_resume)(const struct mtk_cpupm_pwrstate *state);
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void (*mcusys_suspend)(const struct mtk_cpupm_pwrstate *state);
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void (*mcusys_resume)(const struct mtk_cpupm_pwrstate *state);
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int (*invoke)(unsigned int funcID, void *priv);
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};
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int register_cpu_pm_ops(unsigned int fn_flags, struct mtk_cpu_pm_ops *ops);
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int register_cpu_smp_ops(unsigned int fn_flags, struct mtk_cpu_smp_ops *ops);
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struct mt_cpupm_event_data {
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unsigned int cpuid;
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unsigned int pwr_domain;
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};
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/* Extension event for platform driver */
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#if MTK_PUBEVENT_ENABLE
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/* [PUB_EVENT] Core power on */
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_pwr_on, _fn)
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/* [PUB_EVENT] Core power off */
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_pwr_off, _fn)
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/* [PUB_EVENT] Cluster power on */
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_on, _fn)
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/* [PUB_EVENT] Cluster power off */
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_OFF(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_off, _fn)
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/* [PUB_EVENT] Mcusys power on */
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_ON(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_on, _fn)
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/* [PUB_EVENT] Mcusys power off */
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_OFF(_fn) \
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SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_off, _fn)
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#else
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(_fn)
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#define MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(_fn)
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(_fn)
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#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_OFF(_fn)
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_ON(_fn)
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#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_OFF(_fn)
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#endif
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#define MT_PLAT_PWR_STATE_L_CPU (0x0001)
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#define MT_PLAT_PWR_STATE_B_CPU (0x0002)
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#define MT_PLAT_PWR_STATE_L_CLUSTER (0x0101)
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#define MT_PLAT_PWR_STATE_B_CLUSTER (0x0102)
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#define MT_PLAT_PWR_STATE_MCUSYS (0x0701)
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#define MT_PLAT_PWR_STATE_SYSTEM_MEM (0x0f01)
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#define MT_PLAT_PWR_STATE_SYSTEM_PLL (0x0f02)
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#define MT_PLAT_PWR_STATE_SYSTEM_BUS (0x0f03)
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#define MT_PLAT_PWR_STATE_SUSPEND2IDLE (0x1f01)
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#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND (0x1f02)
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#define IS_MT_PLAT_PWR_STATE_MCUSYS(state) (state & 0x400)
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#define IS_MT_PLAT_PWR_STATE_SYSTEM(state) (state & 0x800)
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#define IS_MT_PLAT_PWR_STATE_PLATFORM(state) (state & 0x1800)
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#define PLAT_MT_SYSTEM_SUSPEND PLAT_MAX_OFF_STATE
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#define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE
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#define IS_PLAT_SYSTEM_SUSPEND(aff) (aff == PLAT_MT_SYSTEM_SUSPEND)
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#define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE)
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#define IS_PLAT_SUSPEND2IDLE_ID(stateid) (stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)
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#define IS_PLAT_SUSPEND_ID(stateid) ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) || \
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(stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
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int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops);
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int plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl *ops);
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int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops);
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uintptr_t plat_pm_get_warm_entry(void);
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#endif
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