Jit Loon Lim 3905f57134 feat(intel): setup FPGA interface for Agilex ...

Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5

2022-11-22 23:35:36 +08:00

..

agilex_clock_manager.h

feat(intel): implement timer init divider via cpu frequency. (#1)

2022-05-06 17:37:45 +02:00

agilex_memory_controller.h

intel: Enable bridge access in Intel platform

2020-01-16 10:53:21 +08:00

agilex_mmc.h

plat: intel: set DRVSEL and SMPLSEL for DWMMC

2020-06-08 22:03:34 +00:00

agilex_pinmux.h

feat(intel): setup FPGA interface for Agilex

2022-11-22 23:35:36 +08:00

socfpga_plat_def.h

Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration

2022-05-10 20:17:51 +02:00