Jacky Bai 4bf5019228 fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0 ...

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explicitly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I113069494074194e116fdb1229052d2956bf90ea

2023-02-28 14:26:39 +08:00

..

clock.c

feat(imx8m): add more dram pll setting

2023-02-28 14:26:39 +08:00

ddr4_dvfs.c

feat(imx8m): update the ddr4 dvfs flow to include ddr3l support

2023-02-27 11:22:51 +08:00

dram_retention.c

fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

2023-02-28 14:26:39 +08:00

dram.c

fix(imx8m): fix the current fsp init

2023-02-28 14:26:39 +08:00

lpddr4_dvfs.c

fix(imx8m): fix the dfiphymaster setting after dvfs

2023-02-27 11:23:44 +08:00