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https://github.com/ARM-software/arm-trusted-firmware.git
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bd9344f670
Use full include paths like it is done for common includes.
This cleanup was started in commit d40e0e08283a ("Sanitise includes
across codebase"), but it only cleaned common files and drivers. This
patch does the same to Arm platforms.
Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/tzc_dmc500.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/soc/common/soc_css.h>
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#include <sgm_variant.h>
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/* Is populated with the DMC-500 controllers base addresses */
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static tzc_dmc500_driver_data_t plat_driver_data;
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void plat_sgm_dp_security_setup(void)
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{
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unsigned int nprot_nsaid;
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/*
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* At reset the Mali display processors start with NSAIDs set to zero
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* so the firmware must set them up to the expected values for ARM sgm
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* platforms.
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*/
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nprot_nsaid = mmio_read_32(MALI_DP_BASE + DP_NPROT_NSAID_OFFSET);
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nprot_nsaid &= ~((0xF << W_NPROT_NSAID_SHIFT) |
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(0xF << LS_NPORT_NSAID_SHIFT));
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nprot_nsaid |= ((TZC_NSAID_DISP1 << W_NPROT_NSAID_SHIFT) |
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(TZC_NSAID_DISP0 << LS_NPORT_NSAID_SHIFT));
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mmio_write_32(MALI_DP_BASE + DP_NPROT_NSAID_OFFSET, nprot_nsaid);
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}
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void plat_arm_security_setup(void)
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{
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unsigned int i;
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unsigned int part_num = GET_PLAT_PART_NUM;
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INFO("part_num: 0x%x\n", part_num);
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/*
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* Initialise plat_driver_data with platform specific DMC_BASE
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* addresses
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*/
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switch (part_num) {
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case SGM775_SSC_VER_PART_NUM:
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for (i = 0; i < SGM775_DMC_COUNT; i++)
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plat_driver_data.dmc_base[i] = PLAT_ARM_TZC_BASE
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+ SGM_DMC_SIZE * i;
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plat_driver_data.dmc_count = SGM775_DMC_COUNT;
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break;
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default:
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/* Unexpected platform */
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ERROR("Unexpected platform\n");
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panic();
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}
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/* Initialize the TrustZone Controller in DMC-500 */
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arm_tzc_dmc500_setup(&plat_driver_data, NULL);
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/* Do DP NSAID setup */
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plat_sgm_dp_security_setup();
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/* Do ARM CSS SoC security setup */
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soc_css_security_setup();
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}
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