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f5c58af653
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
56 lines
2.1 KiB
C
56 lines
2.1 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/css/common/css_pm.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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const unsigned char tc0_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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PLAT_MAX_CPUS_PER_CLUSTER,
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return tc0_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
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};
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/*******************************************************************************
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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******************************************************************************/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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{
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return PLAT_MAX_CPUS_PER_CLUSTER;
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}
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#if ARM_PLAT_MT
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/******************************************************************************
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* Return the number of PE's supported by the CPU.
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*****************************************************************************/
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unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
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{
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return PLAT_MAX_PE_PER_CPU;
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}
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#endif
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