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This patch unifies the bakery lock api's across coherent and normal memory implementation of locks by using same data type `bakery_lock_t` and similar arguments to functions. A separate section `bakery_lock` has been created and used to allocate memory for bakery locks using `DEFINE_BAKERY_LOCK`. When locks are allocated in normal memory, each lock for a core has to spread across multiple cache lines. By using the total size allocated in a separate cache line for a single core at compile time, the memory for other core locks is allocated at link time by multiplying the single core locks size with (PLATFORM_CORE_COUNT - 1). The normal memory lock algorithm now uses lock address instead of the `id` in the per_cpu_data. For locks allocated in coherent memory, it moves locks from tzfw_coherent_memory to bakery_lock section. The bakery locks are allocated as part of bss or in coherent memory depending on usage of coherent memory. Both these regions are initialised to zero as part of run_time_init before locks are used. Hence, bakery_lock_init() is made an empty function as the lock memory is already initialised to zero. The above design lead to the removal of psci bakery locks from non_cpu_power_pd_node to psci_locks. NOTE: THE BAKERY LOCK API WHEN USE_COHERENT_MEM IS NOT SET HAS CHANGED. THIS IS A BREAKING CHANGE FOR ALL PLATFORM PORTS THAT ALLOCATE BAKERY LOCKS IN NORMAL MEMORY. Change-Id: Ic3751c0066b8032dcbf9d88f1d4dc73d15f61d8b
180 lines
6.3 KiB
C
180 lines
6.3 KiB
C
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bakery_lock.h>
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#include <cpu_data.h>
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#include <platform.h>
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#include <string.h>
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/*
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* Functions in this file implement Bakery Algorithm for mutual exclusion with the
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* bakery lock data structures in coherent memory.
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*
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* ARM architecture offers a family of exclusive access instructions to
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* efficiently implement mutual exclusion with hardware support. However, as
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* well as depending on external hardware, the these instructions have defined
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* behavior only on certain memory types (cacheable and Normal memory in
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* particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases
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* in trusted firmware are such that mutual exclusion implementation cannot
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* expect that accesses to the lock have the specific type required by the
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* architecture for these primitives to function (for example, not all
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* contenders may have address translation enabled).
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*
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* This implementation does not use mutual exclusion primitives. It expects
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* memory regions where the locks reside to be fully ordered and coherent
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* (either by disabling address translation, or by assigning proper attributes
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* when translation is enabled).
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*
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* Note that the ARM architecture guarantees single-copy atomicity for aligned
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* accesses regardless of status of address translation.
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*/
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#define assert_bakery_entry_valid(entry, bakery) do { \
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assert(bakery); \
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assert(entry < BAKERY_LOCK_MAX_CPUS); \
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} while (0)
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/* Obtain a ticket for a given CPU */
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static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me)
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{
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unsigned int my_ticket, their_ticket;
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unsigned int they;
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/* Prevent recursive acquisition */
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assert(!bakery_ticket_number(bakery->lock_data[me]));
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/*
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* Flag that we're busy getting our ticket. All CPUs are iterated in the
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* order of their ordinal position to decide the maximum ticket value
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* observed so far. Our priority is set to be greater than the maximum
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* observed priority
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*
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* Note that it's possible that more than one contender gets the same
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* ticket value. That's OK as the lock is acquired based on the priority
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* value, not the ticket value alone.
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*/
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my_ticket = 0;
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bakery->lock_data[me] = make_bakery_data(CHOOSING_TICKET, my_ticket);
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for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
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their_ticket = bakery_ticket_number(bakery->lock_data[they]);
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if (their_ticket > my_ticket)
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my_ticket = their_ticket;
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}
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/*
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* Compute ticket; then signal to other contenders waiting for us to
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* finish calculating our ticket value that we're done
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*/
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++my_ticket;
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bakery->lock_data[me] = make_bakery_data(CHOSEN_TICKET, my_ticket);
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return my_ticket;
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}
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/*
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* Acquire bakery lock
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*
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* Contending CPUs need first obtain a non-zero ticket and then calculate
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* priority value. A contending CPU iterate over all other CPUs in the platform,
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* which may be contending for the same lock, in the order of their ordinal
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* position (CPU0, CPU1 and so on). A non-contending CPU will have its ticket
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* (and priority) value as 0. The contending CPU compares its priority with that
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* of others'. The CPU with the highest priority (lowest numerical value)
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* acquires the lock
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*/
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void bakery_lock_get(bakery_lock_t *bakery)
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{
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unsigned int they, me;
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unsigned int my_ticket, my_prio, their_ticket;
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unsigned int their_bakery_data;
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me = plat_my_core_pos();
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assert_bakery_entry_valid(me, bakery);
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/* Get a ticket */
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my_ticket = bakery_get_ticket(bakery, me);
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/*
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* Now that we got our ticket, compute our priority value, then compare
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* with that of others, and proceed to acquire the lock
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*/
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my_prio = PRIORITY(my_ticket, me);
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for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) {
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if (me == they)
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continue;
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/* Wait for the contender to get their ticket */
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do {
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their_bakery_data = bakery->lock_data[they];
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} while (bakery_is_choosing(their_bakery_data));
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/*
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* If the other party is a contender, they'll have non-zero
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* (valid) ticket value. If they do, compare priorities
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*/
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their_ticket = bakery_ticket_number(their_bakery_data);
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if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) {
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/*
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* They have higher priority (lower value). Wait for
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* their ticket value to change (either release the lock
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* to have it dropped to 0; or drop and probably content
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* again for the same lock to have an even higher value)
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*/
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do {
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wfe();
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} while (their_ticket ==
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bakery_ticket_number(bakery->lock_data[they]));
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}
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}
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/* Lock acquired */
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}
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/* Release the lock and signal contenders */
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void bakery_lock_release(bakery_lock_t *bakery)
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{
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unsigned int me = plat_my_core_pos();
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assert_bakery_entry_valid(me, bakery);
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assert(bakery_ticket_number(bakery->lock_data[me]));
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/*
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* Release lock by resetting ticket. Then signal other
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* waiting contenders
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*/
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bakery->lock_data[me] = 0;
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dsb();
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sev();
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}
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