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https://github.com/ARM-software/arm-trusted-firmware.git
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0108047ae4
The common topology description helper funtions and macros for ARM Standard platforms assumed a dual cluster system. This is not flexible enough to scale to multi cluster platforms. This patch does the following changes for more flexibility in defining topology: 1. The `plat_get_power_domain_tree_desc()` definition is moved from `arm_topology.c` to platform specific files, that is `fvp_topology.c` and `juno_topology.c`. Similarly the common definition of the porting macro `PLATFORM_CORE_COUNT` in `arm_def.h` is moved to platform specific `platform_def.h` header. 2. The ARM common layer porting macros which were dual cluster specific are now removed and a new macro PLAT_ARM_CLUSTER_COUNT is introduced which must be defined by each ARM standard platform. 3. A new mandatory ARM common layer porting API `plat_arm_get_cluster_core_count()` is introduced to enable the common implementation of `arm_check_mpidr()` to validate MPIDR. 4. For the FVP platforms, a new build option `FVP_NUM_CLUSTERS` has been introduced which allows the user to specify the cluster count to be used to build the topology tree within Trusted Firmare. This enables Trusted Firmware to be built for multi cluster FVP models. Change-Id: Ie7a2e38e5661fe2fdb2c8fdf5641d2b2614c2b6b
206 lines
6.5 KiB
C
206 lines
6.5 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLAT_ARM_H__
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#define __PLAT_ARM_H__
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#include <bakery_lock.h>
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#include <bl_common.h>
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#include <cassert.h>
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#include <cpu_data.h>
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#include <stdint.h>
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#include <xlat_tables.h>
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#define ARM_CASSERT_MMAP \
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CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \
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<= MAX_MMAP_REGIONS, \
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assert_max_mmap_regions);
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/*
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* Utility functions common to ARM standard platforms
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*/
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void arm_configure_mmu_el1(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit
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#if USE_COHERENT_MEM
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, unsigned long coh_start,
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unsigned long coh_limit
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#endif
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);
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void arm_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit
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#if USE_COHERENT_MEM
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, unsigned long coh_start,
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unsigned long coh_limit
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#endif
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);
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#if IMAGE_BL31
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/*
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* Use this macro to instantiate lock before it is used in below
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* arm_lock_xxx() macros
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*/
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#define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock);
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/*
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* These are wrapper macros to the Coherent Memory Bakery Lock API.
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*/
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#define arm_lock_init() bakery_lock_init(&arm_lock)
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#define arm_lock_get() bakery_lock_get(&arm_lock)
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#define arm_lock_release() bakery_lock_release(&arm_lock)
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#else
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/*
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* Empty macros for all other BL stages other than BL31
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*/
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#define ARM_INSTANTIATE_LOCK
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#define arm_lock_init()
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#define arm_lock_get()
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#define arm_lock_release()
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#endif /* IMAGE_BL31 */
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#if ARM_RECOM_STATE_ID_ENC
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define ARM_LOCAL_PSTATE_WIDTH 4
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#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
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/* Macros to construct the composite power state */
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/* Make composite power state parameter till power level 0 */
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#if PSCI_EXTENDED_STATE_ID
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#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
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#else
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#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#endif /* __PSCI_EXTENDED_STATE_ID__ */
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/* Make composite power state parameter till power level 1 */
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#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
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arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/* Make composite power state parameter till power level 2 */
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#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
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arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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/* IO storage utility functions */
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void arm_io_setup(void);
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/* Security utility functions */
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void arm_tzc_setup(void);
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/* Systimer utility function */
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void arm_configure_sys_timer(void);
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/* PM utility functions */
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int arm_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state);
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int arm_validate_ns_entrypoint(uintptr_t entrypoint);
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void arm_system_pwr_domain_resume(void);
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void arm_program_trusted_mailbox(uintptr_t address);
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/* Topology utility function */
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int arm_check_mpidr(u_register_t mpidr);
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/* BL1 utility functions */
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void arm_bl1_early_platform_setup(void);
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void arm_bl1_platform_setup(void);
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void arm_bl1_plat_arch_setup(void);
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/* BL2 utility functions */
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void arm_bl2_early_platform_setup(meminfo_t *mem_layout);
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void arm_bl2_platform_setup(void);
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void arm_bl2_plat_arch_setup(void);
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uint32_t arm_get_spsr_for_bl32_entry(void);
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uint32_t arm_get_spsr_for_bl33_entry(void);
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/* BL2U utility functions */
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void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
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void *plat_info);
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void arm_bl2u_platform_setup(void);
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void arm_bl2u_plat_arch_setup(void);
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/* BL31 utility functions */
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void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2);
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void arm_bl31_platform_setup(void);
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void arm_bl31_plat_runtime_setup(void);
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void arm_bl31_plat_arch_setup(void);
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/* TSP utility functions */
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void arm_tsp_early_platform_setup(void);
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/* FIP TOC validity check */
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int arm_io_is_toc_valid(void);
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/*
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* Mandatory functions required in ARM standard platforms
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*/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
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void plat_arm_gic_driver_init(void);
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void plat_arm_gic_init(void);
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void plat_arm_gic_cpuif_enable(void);
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void plat_arm_gic_cpuif_disable(void);
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void plat_arm_gic_pcpu_init(void);
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void plat_arm_security_setup(void);
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void plat_arm_pwrc_setup(void);
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void plat_arm_interconnect_init(void);
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void plat_arm_interconnect_enter_coherency(void);
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void plat_arm_interconnect_exit_coherency(void);
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/*
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* Optional functions required in ARM standard platforms
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*/
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void plat_arm_io_setup(void);
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int plat_arm_get_alt_image_source(
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unsigned int image_id,
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uintptr_t *dev_handle,
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uintptr_t *image_spec);
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unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
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const mmap_region_t *plat_arm_get_mmap(void);
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#endif /* __PLAT_ARM_H__ */
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