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26123ca353
The new Allwinner H616 SoC lacks the management controller and the secure SRAM A2, so we need to tweak the memory map quite substantially: We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our compressed virtual address space (max 256MB) anymore, so we revert to the full 32bit VA space and use a flat mapping throughout all of it. The missing controller also means we need to always use the native PSCI ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC. Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| .. | ||
| about | ||
| components | ||
| design | ||
| design_documents | ||
| getting_started | ||
| perf | ||
| plat | ||
| process | ||
| resources | ||
| security_advisories | ||
| change-log-upcoming.rst | ||
| change-log.rst | ||
| conf.py | ||
| global_substitutions.txt | ||
| glossary.rst | ||
| index.rst | ||
| license.rst | ||
| Makefile | ||
| requirements.txt | ||