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1552df5d25
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of timer management, including watchdog, srtc and system counter etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for timer operation. This patch adds timer IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
21 lines
384 B
C
21 lines
384 B
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SCI_H
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#define SCI_H
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/* Defines */
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/* Includes */
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#include <sci/sci_ipc.h>
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#include <sci/svc/pad/sci_pad_api.h>
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#include <sci/svc/pm/sci_pm_api.h>
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#include <sci/svc/rm/sci_rm_api.h>
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#include <sci/svc/timer/sci_timer_api.h>
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#endif /* SCI_H */
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