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https://github.com/ARM-software/arm-trusted-firmware.git
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08438e24e1
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
93 lines
3.4 KiB
C
93 lines
3.4 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include <memctrl.h>
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#include <tegra_def.h>
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/*
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* Init SMMU.
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*/
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void tegra_memctrl_setup(void)
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{
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Configuring SMMU\n");
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/* allow translations for all MC engines */
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY);
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tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL);
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tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL);
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/* flush PTC and TLB */
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tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL);
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL);
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/* enable SMMU */
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tegra_mc_write_32(MC_SMMU_CONFIG_0,
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MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE);
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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}
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/*
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* Secure the BL31 DRAM aperture.
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*
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* phys_base = physical base of TZDRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Configuring TrustZone DRAM Memory Carveout\n");
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tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base);
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tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
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}
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