Olivier Deprez 04825031b2 fix(cm): add barrier before el3 ns exit ...

In cm_prepare_el3_exit_ns, SCR_EL3.NS bit change (to non-secure) is not
committed before the EL2 restoration sequence happens.
At ICC_SRE_EL2 write in cm_el2_sysregs_context_restore, NS is still 0
from CPU perspective (with EEL2=0) which is an invalid condition and
triggers a fault. By adding ISB, SCR_EL3 gets synced with NS=1/EEL2=0
before ICC_SRE_EL2 write.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie72a6152aa7729e66b3344c1b7b0749f54cafb6f

2022-05-09 17:41:29 +02:00

..

aarch32

refactor(context mgmt): add cm_prepare_el3_exit_ns function

2022-04-12 17:42:11 +02:00

aarch64

fix(cm): add barrier before el3 ns exit

2022-05-09 17:41:29 +02:00

cpu_data_array.c

Sanitise includes across codebase

2019-01-04 10:43:17 +00:00