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Cortex-A78C erratum 1827440 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[2], which forces atomic store operations to write-back memory to be performed in the L1 data cache. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7