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3 Commits

Author SHA1 Message Date
Dimitris Papastamos
040b546e94 Implement Cortex-Ares 1043202 erratum workaround 
The workaround uses the instruction patching feature of the Ares cpu.

Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
 2018-06-08 11:46:31 +01:00
Dimitris Papastamos
08268e27ab Add AMU support for Cortex-Ares 
Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
 2018-06-08 11:46:31 +01:00
Isla Mitchell
abbffe98ed Add support for Cortex-Ares and Cortex-A76 CPUs 
Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU).  The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are simple.

Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
 2018-06-08 11:46:31 +01:00