* changes:
fix(versal-net): enable wake interrupt during client suspend
fix(versal-net): disable wakeup interrupt during client wakeup
fix(versal-net): clear power down bit during wakeup
fix(versal-net): fix setting power down state
fix(versal-net): clear power down interrupt status before enable
fix(versal-net): resolve misra rule 20.7 warnings
fix(versal-net): resolve misra 10.6 warnings
Versal uses PLM in the boot flow and printing FSBL in the log for
handoff parameters is misleading. Print proper source of TF-A
handoff parameters.
Change-Id: I331e2eac2f5d30beed8573940ae02094254a759b
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Wakeup interrupt should be set during power down sequence to wake
processor. So enable wakeup interrupt during power down sequence.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I1154495c25e0468496f6e112996fd182aa516d88
Clear and disable wakeup interrupt during client wakeup to avoid
multiple wakeup events.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Iebc644ae582da03001830b96e3190fce10dbac42
Power down bit and power down interrupt needs to be cleared once core
is wakeup to avoid unnecessary power down events. So disable power down
interrupt and clear power down bit during client wakeup.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I3445991692c441831e4ea8dae112e23b19f185a9
Versal NET is supporting max power state to AFF_LVL_2 so set power state
for all affinity level instead of setting for only AFF_LVL_0.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I55a91e798b7566d2f34d7cb1fe28ca25993a7d8e
Currently power down interrupt status is set by default before its
getting enabled. Because of that Linux is getting crashed since its
triggering interrupt before core goes to WFI state. So clear interrupt
status before enabling power down interrupt.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ia8d047b6078a49ab3dbe3e0bf24422357f0138c2
Fix below MISRA violation from versal_net_def.h:
- MISRA Violation: MISRA-C:2012 R.10.6:
- Macro parameter expands into an expression without being wrapped
by parentheses.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ie365d24c02bb38163005a3c073642d5c96412e2d
Fix below MISRA violation from versal_net_def.h:
- MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an
object with wider essential type
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I74f8e5d63523f33d245a21f8e4f04d30e40b05e7
OEN Number 48 to 63 is for Trusted App and OS.
GET_SMC_OEN limits the return value of OEN number to 63 by bitwise AND
operation with 0x3F. Thus the upper limit check for OEN value returned
by GET_SMC_OEN is not required.
Removing the upper limit check for the OEN value returned by GET_SMC_OEN
resolves integer handling issue CONSTANT_EXPRESSION_RESULT
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: Ie04a4e2fb7cc85ec6055a5662736a805a89f7085
There is no reason to use macros from trusty spd header and creating
dependency on it. Use directly macros from lib/smccc.h
Co-developed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I7cf1f76a5358ffc297c914f41c437469f5a42411
The api_version is checked in pm_setup() and an error is returned. The
smc handlers will not be registered on error so doing the check again is
redundant. This also silences a warning when compiling with -Wextra.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I09395e6a20e3f6eb22a1f81ec2f6bdf034eeb4bf
TF-A wants to eventually enable -Wold-style-definition globally. Convert
the rare few instances where this is still the case.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9c450fc875cf097e6de2ed577ea3b085821c9f5e
MISRA Violation: MISRA C-2012 Rule 7.2
- Initialize the unsigned int with value 0u in pm_service component.
Current misra warning detection tool is not reporting this as
warning. It reports only when the initialized value exceeds the
range of data type based on compiler used.
But, this change is added as a part of precaution as some other
misra checker tool may report it as violation of rule 7.2.
Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I50a5cee2a077fe157e79757d959ce33064225af3
MISRA Violation: MISRA C-2012 Rule 17.7
- Check the return status of function pm_get_api_version
and return error in case of failure.
Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I69fb000c04f22996da7965a09a1797c7bfaad252
Remove zeromem function as the array is already initialized
with value 0.
MISRA Violation: MISRA C-2012 Rule 9.1
- Initialize the array/variable with a value 0 to resolve
the misra warnings in pm_service component.
Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I1a3d44a7ae4088a3034eb0119d82b99cd4617ccd
TF-A is reporting that erratum are missing to be enabled.
Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_1941500
ERRATA_A78_AE_1951502
ERRATA_A78_AE_2376748
ERRATA_A78_AE_2395408
For further information refer to
https://developer.arm.com/documentation/SDEN1707912/1300/
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Ib7fc16e035feab1dfbd88c1f8ce128b057eee86d
TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.
For futher information please refer to
https://developer.arm.com/documentation/epm012079/11/
where
859971 is "Speculative instruction prefetch to Execute-never (XN) memory
could cause deadlock or data integrity issue" and
1319367 is "Speculative AT instruction using out-of-context translation
regime could cause subsequent request to generate an incorrect
translation".
Change-Id: I408706713a169e53db63ac5657751b0b003e646d
Signed-off-by: Michal Simek <michal.simek@amd.com>
The purpose of this code is to extract api_id from smc_fid but this masking
is done already in the code with using generic mask from smccc.h
(FUNCID_NUM_MASK). That's why remove FUNCID_MASK is which not needed and
actually also equal to already used FUNCID_NUM_MASK.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I1113825baa5d9d58d9d7c5d9d5855fecf62e8d45
MISRA Violation: MISRA-C: 2012 R.10.1
- The operand to the operator does not have an essentially
unsigned type.
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Change-Id: I0f974e9d6f63dddfab55d55c952a57645d931e40
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
Change-Id: I3779f7b6e074e33cb66ace3bef2117029badce1e
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.
Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568
QEMU COSIM platform is equivalent to qemu with additional cosim
extensions, so just switching platform_id to QEMU if QEMU_COSIM is
detected.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I922d10b1605c7f900158fa7fbe82571d3b9d4792
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149
Add support to send IPI to firmware.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd54c05b6a726e0d398dfc1cdcc7f4cf09ba725
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Change-Id: Id85e69b29b124052b4a87462ce27fcdfc00c13c9
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.
Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60
If primary core is down, then IPI interrupt should be
routed to another core for processing.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471
* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main
Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9
Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0
pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf
Add missing space in one line comment to follow common coding style.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0
%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817
Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b57 ("fix(zynqmp): resolve misra R14.4 warnings").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd
GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be
The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.
Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24
