Move the definition of DT_UART_COMPAT in stm32mp1_def.h to be used
in several files.
Change-Id: I74d0350bcd971df9b15697f2b9ec04061d6a7656
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
Update the FIP load address and size for serial boot to support
product with a DDR size = 128MB
1/ Move the FIP location at the end of the first 128MB
2/ Reduce the DWL_BUFFER_SIZE to 16MB, to be coherent with the value
indicated in USB enumeration
- for STM32MP13x: "@SSBL /0x03/1*16Me"
- for STM32MP15x: "@Partition3 /0x03/1*16Me"
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id93bf00c64832c17426bfd78e060861275677ecc
Add the possibility to configure the UART baudrate; reused the
console configuration, defined in STM32MP_UART_BAUDRATE.
The default value remains 115200.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifcf2b36e8ac929265405bc88e824ee78be3b5bbb
The parameter over_sampling of stm32_uart_init_s is not required
as it can be computed dynamically from clock rate of the serial
device and the requested baudrate.
Oversampling by 8 is allowed only for higher speed
(up to clock_rate / 8) to reduce the maximum receiver tolerance
to clock deviation.
This patch update the driver, the serial init struct and the
only user, the stm32cubeprogrammer over uart support.
Change-Id: I422731089730a288defeb7fa49886db65d0902b2
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8d79969c003a984675cbe705de890b51a1f7f4ea
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I11c2672a1089f24a9fafcf6555b8e1d52032cfde
It is more suitable to place platform_def.h in mt8188/include.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I35720690ff4f2ca99c9430edb8bbe17edf9aefb9
Add MCUSYS drivers support for MT8188.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I84107702a9fd021c37d2997ad25b321a483a1a66
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.
TEST=build pass.
BUG=b:244216434
Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com>
Change-Id: I468036131e941a46bc1ec12d33105146000730d8
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I131354d72bbc190af504e9639bcc85a720e2bb17
To use power manager function more easier, we add some drivers to let
the implementation easier.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: Ibc6e1680c4534592ed37de49da39b6667f468ea1
To support more LPM feature, we add more options for build helper.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Change-Id: I17eeedbe0674e321f1891074ba0c72d858841dae
We are not using cold_boot.[c|h] for mt8188, so remove them first.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I721aca37d5fb422f274bb1ab46150e1eddf7c480
We should wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE to avoid
build error.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idfd760fbb7c782d4fc9de674d86a7123e0129c0d
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.
Signed-off-by: Claus Pedersen <claustbp@google.com>
Change-Id: Icc201ea7b63c1277e423c1cfd13fd6816c2bc568
QEMU COSIM platform is equivalent to qemu with additional cosim
extensions, so just switching platform_id to QEMU if QEMU_COSIM is
detected.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I922d10b1605c7f900158fa7fbe82571d3b9d4792
Increase the max possible size of BL33 from 1MB to 2MB.
For example, edk2 is usually bigger than 1MB
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Change-Id: Idd4762e25e623de145c65f31cf2dfe1fee466a74
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149
Add support to send IPI to firmware.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd54c05b6a726e0d398dfc1cdcc7f4cf09ba725
CAAM provides serial output during initialization, but the serial init
occurs after CAAM. This leads to serial output produced by CAAM init
function to be omitted and not displayed.
Change the order of initialization and call CAAM init after Serial. This
has no impact as Serial does not require CAAM to be initialized upfront.
Fixes: 2502709f60 ("plat: imx8m: Add caam module init on imx8m")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I09c0a5474a1babfb0b53c4455891689ec08b5bdb
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
Serial output is missing the EOL marker, which makes the output garbled.
Add EOL to the output, which adds a newline and makes log output
consistent.
Fixes: 77850c96f2 ("feat(plat/imx8m): do not release JR0 to NS if HAB is using it")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Franck LENORMAND <franck.lenormand@nxp.com>
Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I58b67f441016122bc9361d7224d310522917eff0
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Change-Id: Id85e69b29b124052b4a87462ce27fcdfc00c13c9
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>
ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.
Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60
To fix that response should not be NULL when there is response data
need to be sent to input buffer by SDM.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id70289521792f5f995456d2e67e18f0185ca3fc0
To fix that the response data is returned when the source size ready
is still fit for response data size.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id8924137a5c33888e7042e9ab0e0e8c49b4a41ed
Enable the CSS implementation of the warm reset for the rdn2 platform.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I75128d8bbcccbc26cf1e904691c7ef71349c622f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I547253ee28ef7eefa78180d016893671a406bbfa
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
Change-Id: I4917dfdc47be5ce7367bee629486a6344cdd706f
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
If primary core is down, then IPI interrupt should be
routed to another core for processing.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471
This patch adds two helper functions:
- plat_ic_raise_ns_sgi to raise a NS SGI
- plat_ic_raise_s_el1_sgi to raise a S-EL1 SGI
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I6f262dd1da1d77fec3f850eb74189e726b8e24da
* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main
Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9
Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0
pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf
Add missing space in one line comment to follow common coding style.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0
%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817
Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b1772 ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b ("fix(zynqmp): resolve misra R14.4 warnings").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd
GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be
The commit 389594dfa7 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.
Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24
Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Acked-by: Tanmay Shah <tanmay.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0
Some registers of MSDC need to be set in ATF, so we add MSDC drivers.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idde51a136ad08dbaece0bdaa804b934fca7046b6
- MTK_SIP_KERNEL_DFD can be moved to mtk_sip_def.h.
- Remove unused MTK_SIP_* definations which are already defined in
mtk_sip_def.h.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ife8f1e842d986691488548632426f194199d42b9
Renesas platform does not support crypto, but mbedtls_common.mk
is still included in its makefile. Therefore, this inclusion
was removed to avoid un-necessary compilation of mbedTLS source.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib6978255e39a7f5d5013952841930ae68b12c318
When putting FIP binary in eMMC boot partition (with STM32MP_EMMC_BOOT),
the FIP max size should be precised. If it is not, an assert fails in
io_block driver, as cur->size will be zero.
For this length, we then use the size of the eMMC boot partition minus
STM32MP_EMMC_BOOT_FIP_OFFSET.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I48b7635cff64f52d4b337a4c8c3becd9a0be72e8
* changes:
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
fix(n1sdp): add numa node id for pcie controllers
fix(n1sdp): replace non-inclusive terms from dts file
* changes:
feat(stm32mp1): allow to override MTD base offset
feat(stm32mp1): manage second NAND OTP on STM32MP13
feat(stm32mp1): add define for external scratch buffer for nand devices
feat(mtd): add platform function to allow using external buffer
feat(libc): introduce __maybe_unused
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move pmic.[c|h] to common folder
refator(mediatek): move common definitions of pmic wrap to common folder
feat(mt8188): add IOMMU enable control in SiP service
feat(mt8188): add display port control in SiP service
fix(mediatek): use uppercase for definition
feat(mediatek): move dp drivers to common folder
feat(mediatek): move mtk_cirq.c drivers to cirq folder
feat(mt8188): initialize GIC
feat(mt8188): initialize systimer
feat(mt8188): initialize platform for MediaTek MT8188
refator(mediatek): remove unused files
refator(mediatek): move drivers folder in common to plat/mediatek
feat(mediatek): support coreboot BL31 loading
TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I348eff0f53341593f74a63780e2e8298cbc3ec88
Add PWRAP and PMIC driver to support power-off.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: Id9951134925f6cb5f8d304a7b8e7901837809bd9
These two files are identical on MT8192 and MT8195. They can also be
used on MT8188. So move them to common/drivers/pmic/.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c12d15f1da79ab5767ac02b3ab70e8508155ee8
Some definitions can be shared among mt8192, mt8195, and
mt8186, so move them to pmic_wrap_init_common.h.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I992b61a47a84039fe8c246e2ff75721c57ee41a5
Add SiP service for multimedia & infra master to enable/disable
MM & INFRA IOMMU in secure world
TEST=build pass
BUG=b:236339614
Signed-off-by: Chengci Xu <chengci.xu@mediatek.corp-partner.google.com>
Change-Id: I4eb1fda6044cf2cb6c22c005cb2fa550906b71e9
MTK display port mute/unmute control registers need to be
set in secure world.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0aa0675f07c80aab4349493bfbb0782bf0bbef58
Display port driver can be reused, so we move it to common/drivers.
TEST=build mt8195 pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I58c7b41ba3ad653cdf6f6fbae6778abfd7e950a9
To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h
to common/drivers/cirq.
We also rename mtk_cirq.c/h to mt_cirq.c/h for consistency with other
driver folders.
TEST=build pass for mt8192/mt8195/mt8186
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71bc442f00b16fb4031260937982c0496fcaaea0
We do not use oem_svc.[c|h], so remove them.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0afb64d997cf4e23063f4fa2226e8d2649d22574
We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6b344e660f40a23b15151aab073d3045b28f52aa
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a
* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ie899c512b11fd7c4312e3a808bb6b9d2376cdb8c
The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I45e95ea51e90158187452eba52fc58090d1c60a4
The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration is introduced to support quad core clusters on the J784S4
SoC of the K3 family of devices.
See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Change-Id: I0ed1f14ab32a56ae06e3df3161ace4597d14a48d
Implement mandatory platform port functions. Receive
boot arguments from bl2, populate bl33 and bl32 image
entry structs, call each MTK initcall levels
in these mandatory platform port functions.
After bl31_main exit and handover to 2nd boot loader,
mtk bl33 issues SMC and traps to TF-A to execute boot_to_kernel
and then handover to Linux kernel.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8d5a3511668fc749c4c71edf1ac700002cb5a9c8
To modularize SMC handler, provide macro function in mtk_sip_svc.h.
Drivers register SMC name with value in mtk_sip_def.h, and bind the SMC
handler with the SMC ID by calling DECLARE_SMC_HANDLER macro.
MTK_SIP_SMC_FROM_BL33_TABLE expand the SMC table as switch-case table
statically. DECLARE_SMC_HANDLER wrap SMC handlers with a structure and
put in a section.
During cold boot initialization, in MTK_EARLY_PLAT_INIT level parse the
section to assign each handler with an index. Each SMC request can be
identified with switch-case and take the index to call into
corresponding SMC handler.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I03da212c786de0ec0ea646ba906065ecfcd82571
Provide six initcall levels for drivers/modules initialize HW
controllers or runtime arguments during cold boot.
The initcall level cold boot execution order:
-MTK_EARLY_PLAT_INIT
Call before MMU enabled.
-MTK_ARCH_INIT
MMU Enabled, arch related init(GiC init, interrupt type registration).
-MTK_PLAT_SETUP_0_INIT
MTK driver init level 0.
-MTK_PLAT_SETUP_1_INIT
MTK driver init level 1.
-MTK_PLAT_RUNTIME_INIT
MTK driver init. After this initcall, TF-A handovers to MTK 2nd
bootloader.
-MTK_PLAT_BL33_DEFER_INIT
MTK 2nd bootloader traps to TF-A before handover to rich OS.
This initcall executed in the trap handler(boot_to_kernel).
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: Icd7fe95372441db73c975ccb6ce77a6c529df1cc
Manage MTK SiP SMC ID with macros for 32/64 bit and
function declaration code generation.
Partition SMC ID with different exception level sources.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8966cd94f0d825e7ebae08833d2bd9fceedfd45e
Leverage pubsub event framework to customize vendor's
event for better software modularization instead of adding
call entries in abstraction layer for customized platform function
with wrap-up define.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I48be2303c45f759776fa2baa1c21130c1a8f0fa3
Add an external parameter STM32MP_FORCE_MTD_START_OFFSET that allows to
override the default FIP offset used to read the first programmed image.
It can be used for NOR, RAW_NAND or SPI_NAND boot device.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ibe664aae0e5ee90dd6629e544c9e034d751fffed
On STM32MP13, 2 OTP fuses can be used to configure NAND devices.
By default OTP CFG9 is used for sNAND. A new OTP (CFG10) is used
to configure raw NAND. Thanks to bit 0 of CFG10 OTP, this default
configuration can be switched.
For sNAND on STM32MP13, the NAND_PARAM_STORED_IN_OTP is not used.
The sNAND parameters have to be taken from OTP bits.
Change-Id: Ib95e0f9b9e66179a58b07f723ea01dce68b96475
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Override the default platform function to use an external buffer
on STM32MP13 platform.
It allows to use a temporary buffer located at the SRAM1 memory end.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ibd84bb336c60af24608268916b3a18bb5a0fa3db
* changes:
feat(tsp): enable test cases for EL3 SPMC
feat(tsp): increase stack size for tsp
feat(tsp): add ffa_helpers to enable more FF-A functionality
