Commit Graph

10 Commits

Author SHA1 Message Date
Michal Simek
f114fd3b10 chore(zynqmp): fix comment style in zynqmp_def.h
Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0
2022-09-14 09:35:58 +02:00
Venkatesh Yadav Abbarapu
bfd7c88190 feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The operand to the operator does not have an essentially unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I97bbc056f4fee167742429e144144ba793bf77b3
2022-07-07 10:20:48 +02:00
Venkatesh Yadav Abbarapu
5bcbd2de12 fix(zynqmp): resolve misra 7.2 warnings
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieeff81ed42155c03aebca75b2f33f311279b9ed4
2022-05-06 13:43:34 +05:30
Rajan Vaja
9f0ddae317 plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
2021-04-21 12:29:37 +02:00
Will Wong
0a67923b99 zynqmp: pm: Add support for PS and system reset on WDT restart
Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.

Signed-off-by: Will Wong <willw@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702
2021-01-12 16:59:55 +00:00
Kalyani Akula
d716f045f2 zynqmp : pm : Adds new zynqmp-pm api SMC call for register access
This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.

Signed-off-by: Kalyani Akula <kalyania@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042
2021-01-04 11:50:02 +00:00
Tejas Patel
a7379a2ab1 plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. So, change its name from PM_BOOT_HEALTH_STATUS_REG
to PMU_GLOBAL_GEN_STORAGE4.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I2f5c4c6a161121e7cdb4b9f0f8711d0dad16c372
2020-12-06 21:46:03 -08:00
Manish V Badarkhe
53adebad8b Create separate header for ARM specific SMCCC defines
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header
and include this header in all ARM platforms.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
2020-03-30 12:21:38 +00:00
Mounika Grace Akula
b3ce966ab3 zynqmp: pm: Add LPD WDT clock to the pm_clock structure
This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.

Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403
2020-01-07 15:03:43 -08:00
Jolly Shah
99564393bf plat: xilinx: zynqmp: Move zynqmp_def.h to include directory
Move zynqmp_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of zynqmp_def.h

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
2019-01-09 12:05:56 -08:00