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3 Commits

Author SHA1 Message Date
Michal Simek
0bf622de68 feat(versal-net): add support for IPI 
Add support to send IPI to firmware.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd54c05b6a726e0d398dfc1cdcc7f4cf09ba725
 2022-09-20 19:02:39 +02:00
Michal Simek
8529c7694f feat(versal-net): add SMP support for Versal NET 
Add SMP support for Versal NET via register access.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
 2022-09-20 09:25:32 +02:00
Michal Simek
1d333e6909 feat(versal-net): add support for Xilinx Versal NET platform 
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
 2022-09-20 09:19:43 +02:00