26 Commits

Author SHA1 Message Date
Bo-Chen Chen
80fa75842d refator(mediatek): move pmic.[c|h] to common folder
These two files are identical on MT8192 and MT8195. They can also be
used on MT8188. So move them to common/drivers/pmic/.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c12d15f1da79ab5767ac02b3ab70e8508155ee8
2022-09-05 18:12:24 +08:00
Bo-Chen Chen
ca93b018dc refator(mediatek): move common definitions of pmic wrap to common folder
Some definitions can be shared among mt8192, mt8195, and
mt8186, so move them to pmic_wrap_init_common.h.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I992b61a47a84039fe8c246e2ff75721c57ee41a5
2022-09-05 18:12:24 +08:00
Rex-BC Chen
d150b6296e feat(mediatek): move dp drivers to common folder
Display port driver can be reused, so we move it to common/drivers.

TEST=build mt8195 pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I58c7b41ba3ad653cdf6f6fbae6778abfd7e950a9
2022-09-05 13:53:14 +08:00
Rex-BC Chen
cc76896d9e feat(mediatek): move mtk_cirq.c drivers to cirq folder
To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h
to common/drivers/cirq.

We also rename mtk_cirq.c/h to mt_cirq.c/h for consistency with other
driver folders.

TEST=build pass for mt8192/mt8195/mt8186
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71bc442f00b16fb4031260937982c0496fcaaea0
2022-09-05 13:53:13 +08:00
Edward-JW Yang
ab45305062 feat(plat/mediatek/mt8195): improve SPM wakeup log
To enhance debug efficiency, modify wakeup log:
1. Redefine strings of wakeup reason for readability.
2. Indicate 26M clock on/off state of previous suspend.
3. Add warning log if SPM cannot get wakeup reason.

BUG=b:205201535
TEST=build pass

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Icb14ebb08958da225969abd3cdd9e471d232c7eb
2021-12-13 17:20:37 +08:00
Tinghan Shen
690cb1265e feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204347737
TEST=build pass

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc
2021-12-06 15:29:08 +08:00
Tinghan Shen
20ef588e86 feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2021-12-06 15:29:06 +08:00
Flora Fu
296b590206 feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
2021-11-30 09:34:05 +08:00
Flora Fu
88906b4437 feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e9568c0150436afa42
2021-11-30 09:23:46 +08:00
Madhukar Pappireddy
964ee4e6be fix(mt8195): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit variables.

Change-Id: I09a8d174694d4b170a6ef2e4a03df13adc829c00
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-11-11 12:23:36 -06:00
Edward-JW Yang
c260b3246b feat(plat/mdeiatek/mt8195): remove adsp event from wakeup source
Audio DSP is power-off when system suspend. Remove it from
wakeup source list to prevent unnecessary wakeup.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Id7251de9c8b9c9a4a4b2c41a310168d336035b9a
2021-10-14 19:25:28 +08:00
Rex-BC Chen
3b994a7530 feat(plat/mdeiatek/mt8195): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.

BUG=b:192429713

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
2021-09-28 10:13:47 +08:00
Rex-BC Chen
85e4d14df1 fix(plat/mediatek/mt8195): fix coverity fail
Add break to correct the driver flow.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie20f402d543fbf90172671e007fad30d5dc2ab10
2021-09-17 09:55:21 +08:00
Penny Jan
75edd34ade feat(plat/mediatek/mt8195): add EMI MPU basic drivers
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.

Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
2021-09-15 10:59:14 +08:00
Dawei Chien
d562130ea9 feat(plat/mediatek/mt8195): add vcore-dvfs support
Add DVFSRC init flow.

Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
2021-09-14 10:24:12 +08:00
Garmin Chang
1f81cccedd fix(plat/mediatek/me8195): fix error setting for SPM
There is a error setting for SPM, so we need to fix this issue.

Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57
2021-07-20 02:55:46 +01:00
Garmin Chang
49d3bd8c4c feat(plat/mediatek/mt8195): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.

Change-Id: I3237199bc217bd3682f51d31284db5fd0324b396
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
2021-07-06 14:59:06 +08:00
Edward-JW Yang
859e346b89 feat(plat/mediatek/mt8195): add SPM suspend driver
Support DRAM/MAINPLL/26M off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Ib8502f9b0b4e47aa405e5449f0b6d483bd3f5d77
2021-07-02 16:22:16 +08:00
Edward-JW Yang
d336e093dd feat(plat/mediatek/mt8195): support MCUSYS off when system suspend
Add drivers to support MCUSYS off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
2021-07-02 16:22:16 +08:00
Elly Chiang
048189637e feat(plat/mediatek/mt8195): add support for PTP3
Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.

Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Elly Chiang <elly.chiang@mediatek.com>
2021-07-02 16:22:16 +08:00
Rex-BC Chen
7eb4223757 feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
2021-05-26 02:13:56 +01:00
Yidi Lin
0909819a4f mediatek: mt8195: add power-off support
mt8195 also uses PMIC mt6359p. The only difference is the
pwrap register definition.

Change-Id: I9962263c46187d1344f14f857bf4b51e33aedda0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
2021-04-23 10:00:05 +08:00
mtk20895
aebd4dc8ff mediatek: mt8195: Add gpio driver
Add gpio driver.

Signed-off-by: mtk20895 <zhiqiang.ma@mediatek.com>
Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
2021-04-23 10:00:04 +08:00
James Liao
fe98542843 mediatek: mt8195: Add CPU hotplug and MCDI support
Implement PSCI platform OPs to support CPU hotplug and MCDI.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I1321f7989c8a3d116d698768a7146e8f180ee9c0
2021-04-23 10:00:04 +08:00
James Liao
acc855488e mediatek: mt8195: Add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: I6a6f9bf5d1d8bda1ee603d8bf3fc206437de7ad8
2021-04-23 10:00:04 +08:00
James Liao
0d82eff6fb mediatek: mt8195: Add SPMC driver
Add SPMC driver for CPU power on/off.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Change-Id: If47d7f3f3b9965f3c0402ea6cdb917ad1d16bb32
2021-04-23 10:00:04 +08:00