This patch switches to the functions which identify the underlying
platform in order to calculate the chip SKU.
Change-Id: I20cf5623465289ccfab28d6578efcf762bfeb456
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.
Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes the logic to calculate the higher bits for TZRAM's base/end
addresses.
Fixes coverity error "31853: Wrong operator used (CONSTANT_EXPRESSION_RESULT)"
Change-Id: Iff62ef18cba59cd41ad63a5c71664872728356a8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes the programming logic for the Video memory carveout's
size. The Memory Controller expects the size in terms of MBs instead
of bytes.
Change-Id: Ia8261b737448bae9a435fe21ab336126785d4279
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch removes stream ID override for the Security Engine
hardware block as its stream ID is programmed by the NS world
driver.
Original change by Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: Ia6523c1a1bb0a82bdeb878feb55670813899bdac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled
Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch enables overrides for APE domains to allow the chip verification
software harness (MODS) to execute its test cases.
Original change by Harvey Hsieh <hhsieh@nvidia.com>
Change-Id: I09b22376068c5b65d89c2a53154ccb2c60d955bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.
Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
The memory controller loses its settings when the device enters system
suspend state.
This patch adds a handler to restore the Video Memory settings in the
memory controller, which would be called after exiting the system suspend
state.
Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
For all APE clients (APER, APEW, APEDMAR, APEDMAW) set NO_OVERRIDE
for MC_SID_CFG as ACAST/ADAST will be setup with the required SIDs
ie. 0x7F & 0x1E.
Original change by Nitin Kumbhar <nkumbhar@nvidia.com>
Change-Id: Idec981b3537cc95dac6ec37cdaa38bc45b16d232
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.
Original changes by Alex Waterman <alexw@nvidia.com>
Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
The GPU is the real consumer of the video protected memory region
and it needs to be in reset to pick up the new region.
This patch checks if the GPU is in reset before we program the new
video protected memory region settings.
Change-Id: I44f553bfcf07b1975abad53b245954be966c8aeb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch fixes the incorrect override settings for the SCE
hardware block.
Original change by Pekka Pessi <ppessi@nvidia.com>
Change-Id: I33db55d6004331988b52ca70157aab1409f4829f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch programs the Memory controller's control registers
to disable non-secure accesses to the TZRAM. In case these
registers are already programmed by the BL2/BL30, then the
driver just bails out.
Change-Id: Ia1416988050e3d067296373060c717a260499122
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds driver for the Memory Controller (v2) in the newer
Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of
the proprietary block in the past.
Change-Id: I78359da780dc840213b6e99954e45e34428d4fff
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
