* changes:
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
fix(n1sdp): add numa node id for pcie controllers
fix(n1sdp): replace non-inclusive terms from dts file
* changes:
feat(stm32mp1): allow to override MTD base offset
feat(stm32mp1): manage second NAND OTP on STM32MP13
feat(stm32mp1): add define for external scratch buffer for nand devices
feat(mtd): add platform function to allow using external buffer
feat(libc): introduce __maybe_unused
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move pmic.[c|h] to common folder
refator(mediatek): move common definitions of pmic wrap to common folder
feat(mt8188): add IOMMU enable control in SiP service
feat(mt8188): add display port control in SiP service
fix(mediatek): use uppercase for definition
feat(mediatek): move dp drivers to common folder
feat(mediatek): move mtk_cirq.c drivers to cirq folder
feat(mt8188): initialize GIC
feat(mt8188): initialize systimer
feat(mt8188): initialize platform for MediaTek MT8188
refator(mediatek): remove unused files
refator(mediatek): move drivers folder in common to plat/mediatek
feat(mediatek): support coreboot BL31 loading
TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I348eff0f53341593f74a63780e2e8298cbc3ec88
Add PWRAP and PMIC driver to support power-off.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: Id9951134925f6cb5f8d304a7b8e7901837809bd9
These two files are identical on MT8192 and MT8195. They can also be
used on MT8188. So move them to common/drivers/pmic/.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c12d15f1da79ab5767ac02b3ab70e8508155ee8
Some definitions can be shared among mt8192, mt8195, and
mt8186, so move them to pmic_wrap_init_common.h.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I992b61a47a84039fe8c246e2ff75721c57ee41a5
Add SiP service for multimedia & infra master to enable/disable
MM & INFRA IOMMU in secure world
TEST=build pass
BUG=b:236339614
Signed-off-by: Chengci Xu <chengci.xu@mediatek.corp-partner.google.com>
Change-Id: I4eb1fda6044cf2cb6c22c005cb2fa550906b71e9
MTK display port mute/unmute control registers need to be
set in secure world.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0aa0675f07c80aab4349493bfbb0782bf0bbef58
Display port driver can be reused, so we move it to common/drivers.
TEST=build mt8195 pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I58c7b41ba3ad653cdf6f6fbae6778abfd7e950a9
To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h
to common/drivers/cirq.
We also rename mtk_cirq.c/h to mt_cirq.c/h for consistency with other
driver folders.
TEST=build pass for mt8192/mt8195/mt8186
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71bc442f00b16fb4031260937982c0496fcaaea0
We do not use oem_svc.[c|h], so remove them.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0afb64d997cf4e23063f4fa2226e8d2649d22574
We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6b344e660f40a23b15151aab073d3045b28f52aa
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a
If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-id=0 and
pcie_secondary_ctlr is assigned numa-node-id=1.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I533abdd6ea162df7b15ee04cbfc48ba7a544b91a
* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ie899c512b11fd7c4312e3a808bb6b9d2376cdb8c
The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I45e95ea51e90158187452eba52fc58090d1c60a4
Cortex-A510 erratum 2347730 is a Cat B erratum that affects
revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is
fixed in r1p2. The workaround is to set CPUACTLR_EL1[17]
to 1, which will disable specific microarchitectural clock
gating behaviour.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latesthttps://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I115386284c2d91bd61515142f971e2e72de43e68
The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration is introduced to support quad core clusters on the J784S4
SoC of the K3 family of devices.
See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Change-Id: I0ed1f14ab32a56ae06e3df3161ace4597d14a48d
Currently, when SPMC at S-EL2 is used, we cannot use the RAS framework
to handle Group 0 interrupts. This is required on platforms where first
level of triaging needs to occur at EL3, before forwarding RAS handling
to a secure partition running atop an SPMC (hafnium).
The RAS framework depends on EHF and EHF registers for Group 0
interrupts to be trapped to EL3 when execution is both in secure world
and normal world. However, an FF-A compliant SPMC requires secure
interrupts to be trapped by the SPMC when execution is in S-EL0/S-EL1.
Consequently, the SPMC (hafnium) is incompatible with EHF, since it is
not re-entrant, and a Group 0 interrupt trapped to EL3 when execution is
in secure world, cannot be forwarded to an SP running atop SPMC.
This patch changes EHF to only register for Group 0 interrupts to be
trapped to EL3 when execution is in normal world and also makes it a
valid routing model to do so, when EL3_EXCEPTION_HANDLING is set (when
enabling the RAS framework).
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I72d4cf4d8ecc549a832d1c36055fbe95866747fe
Implement mandatory platform port functions. Receive
boot arguments from bl2, populate bl33 and bl32 image
entry structs, call each MTK initcall levels
in these mandatory platform port functions.
After bl31_main exit and handover to 2nd boot loader,
mtk bl33 issues SMC and traps to TF-A to execute boot_to_kernel
and then handover to Linux kernel.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8d5a3511668fc749c4c71edf1ac700002cb5a9c8
To modularize SMC handler, provide macro function in mtk_sip_svc.h.
Drivers register SMC name with value in mtk_sip_def.h, and bind the SMC
handler with the SMC ID by calling DECLARE_SMC_HANDLER macro.
MTK_SIP_SMC_FROM_BL33_TABLE expand the SMC table as switch-case table
statically. DECLARE_SMC_HANDLER wrap SMC handlers with a structure and
put in a section.
During cold boot initialization, in MTK_EARLY_PLAT_INIT level parse the
section to assign each handler with an index. Each SMC request can be
identified with switch-case and take the index to call into
corresponding SMC handler.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I03da212c786de0ec0ea646ba906065ecfcd82571
Provide six initcall levels for drivers/modules initialize HW
controllers or runtime arguments during cold boot.
The initcall level cold boot execution order:
-MTK_EARLY_PLAT_INIT
Call before MMU enabled.
-MTK_ARCH_INIT
MMU Enabled, arch related init(GiC init, interrupt type registration).
-MTK_PLAT_SETUP_0_INIT
MTK driver init level 0.
-MTK_PLAT_SETUP_1_INIT
MTK driver init level 1.
-MTK_PLAT_RUNTIME_INIT
MTK driver init. After this initcall, TF-A handovers to MTK 2nd
bootloader.
-MTK_PLAT_BL33_DEFER_INIT
MTK 2nd bootloader traps to TF-A before handover to rich OS.
This initcall executed in the trap handler(boot_to_kernel).
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: Icd7fe95372441db73c975ccb6ce77a6c529df1cc
Manage MTK SiP SMC ID with macros for 32/64 bit and
function declaration code generation.
Partition SMC ID with different exception level sources.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8966cd94f0d825e7ebae08833d2bd9fceedfd45e
Leverage pubsub event framework to customize vendor's
event for better software modularization instead of adding
call entries in abstraction layer for customized platform function
with wrap-up define.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I48be2303c45f759776fa2baa1c21130c1a8f0fa3
Add an external parameter STM32MP_FORCE_MTD_START_OFFSET that allows to
override the default FIP offset used to read the first programmed image.
It can be used for NOR, RAW_NAND or SPI_NAND boot device.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ibe664aae0e5ee90dd6629e544c9e034d751fffed
On STM32MP13, 2 OTP fuses can be used to configure NAND devices.
By default OTP CFG9 is used for sNAND. A new OTP (CFG10) is used
to configure raw NAND. Thanks to bit 0 of CFG10 OTP, this default
configuration can be switched.
For sNAND on STM32MP13, the NAND_PARAM_STORED_IN_OTP is not used.
The sNAND parameters have to be taken from OTP bits.
Change-Id: Ib95e0f9b9e66179a58b07f723ea01dce68b96475
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Override the default platform function to use an external buffer
on STM32MP13 platform.
It allows to use a temporary buffer located at the SRAM1 memory end.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ibd84bb336c60af24608268916b3a18bb5a0fa3db
The scratch buffer could be large. The new function allows
platform to defined its own external buffer or use the default
one.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ib7ab8ff19fa0a9cb06e364f058b91af58c3c471a
The node is currently not used in TF-A. Remove it.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f0689f
For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137
The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.
[1] 812daf916c ("feat(st): update the security based on new compatible")
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6
This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition and the
Avenger96 baseboard like it's done in Linux and U-Boot.
Differences to stm32mp157a-avenger96.dts:
- Enable sdmmc2 for booting from eMMC
- improved clock settings like in U-Boot commit b6055945
"ARM: dts: stm32: Adjust PLL4 settings on AV96 again"
- improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74
"ARM: dts: stm32: Synchronize DDR setttings on DH SoMs"
TF-A with this new dts(i) files on this board was fully tested with
the latest OP-TEE developer setup.
Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
