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feat(mt8188): add SPM feature support

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Add SPM low power functions, such as system suspend.

Change-Id: I6d1ad847a81ba9c347ab6fb8a8cb8c69004b7add
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
This commit is contained in:
James Liao 2022-11-16 21:52:21 +08:00 committed by Liju-Clr Chen
parent 45d507599e
commit f299efbea6
14 changed files with 2735 additions and 1 deletions
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171
plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.c Normal file
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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lpm/mt_lpm_smc.h>
#include <mt_spm.h>
#include "mt_spm_rc_api.h"
#include "mt_spm_rc_internal.h"
int spm_rc_condition_modifier(unsigned int id, unsigned int act,
const void *val,
enum mt_spm_rm_rc_type dest_rc_id,
struct mt_spm_cond_tables * const tlb)
{
unsigned int rc_id, cond_id, cond;
int res = 0;
spin_lock(&spm_lock);
rc_id = SPM_RC_UPDATE_COND_RC_ID_GET(id);
cond_id = SPM_RC_UPDATE_COND_ID_GET(id);
do {
if ((dest_rc_id != rc_id) || (val == NULL) || (tlb == NULL)) {
res = -1;
break;
}
cond = *((unsigned int *)val);
if (cond_id < PLAT_SPM_COND_MAX) {
if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
SPM_RC_BITS_SET(tlb->table_cg[cond_id], cond);
} else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
SPM_RC_BITS_CLR(tlb->table_cg[cond_id], cond);
} else {
res = -1;
}
} else if ((cond_id - PLAT_SPM_COND_MAX) < PLAT_SPM_COND_PLL_MAX) {
unsigned int pll_idx = cond_id - PLAT_SPM_COND_MAX;
cond = !!cond;
if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx));
} else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx));
} else {
res = -1;
}
} else {
res = -1;
}
} while (0);
spin_unlock(&spm_lock);
return res;
}
int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
unsigned int act,
enum mt_spm_rm_rc_type dest_rc_id,
struct constraint_status * const src,
struct constraint_status * const dest)
{
if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL) ||
(src == NULL)) {
return -1;
}
spin_lock(&spm_lock);
switch (type) {
case CONSTRAINT_GET_ENTER_CNT:
if (id == MT_RM_CONSTRAINT_ID_ALL) {
dest->enter_cnt += src->enter_cnt;
} else {
dest->enter_cnt = src->enter_cnt;
}
break;
case CONSTRAINT_GET_VALID:
dest->is_valid = src->is_valid;
break;
case CONSTRAINT_COND_BLOCK:
dest->is_cond_block = src->is_cond_block;
dest->all_pll_dump = src->all_pll_dump;
break;
case CONSTRAINT_GET_COND_BLOCK_DETAIL:
dest->cond_res = src->cond_res;
break;
case CONSTRAINT_GET_RESIDNECY:
dest->residency = src->residency;
if (act & MT_LPM_SMC_ACT_CLR) {
src->residency = 0;
}
break;
default:
break;
}
spin_unlock(&spm_lock);
return 0;
}
int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
unsigned int act,
enum mt_spm_rm_rc_type dest_rc_id,
struct constraint_status * const src,
struct constraint_status * const dest)
{
if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
return -1;
}
spin_lock(&spm_lock);
switch (type) {
case CONSTRAINT_UPDATE_VALID:
if (src != NULL) {
if ((act & MT_LPM_SMC_ACT_SET) > 0U) {
SPM_RC_BITS_SET(dest->is_valid, src->is_valid);
} else if ((act & MT_LPM_SMC_ACT_CLR) > 0U) {
SPM_RC_BITS_CLR(dest->is_valid, src->is_valid);
}
}
break;
case CONSTRAINT_RESIDNECY:
if (act & MT_LPM_SMC_ACT_CLR) {
dest->residency = 0;
}
break;
default:
break;
}
spin_unlock(&spm_lock);
return 0;
}
int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
enum mt_spm_rm_rc_type dest_rc_id,
unsigned int valid,
struct constraint_status * const dest)
{
if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
return -1;
}
spin_lock(&spm_lock);
SPM_RC_BITS_SET(dest->is_valid, valid);
spin_unlock(&spm_lock);
return 0;
}
int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
enum mt_spm_rm_rc_type dest_rc_id,
unsigned int valid,
struct constraint_status * const dest)
{
if (((id != MT_RM_CONSTRAINT_ID_ALL) && (id != dest_rc_id)) || (dest == NULL)) {
return -1;
}
spin_lock(&spm_lock);
SPM_RC_BITS_CLR(dest->is_valid, valid);
spin_unlock(&spm_lock);
return 0;
}

45
plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_api.h Normal file
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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_RC_API_H
#define MT_SPM_RC_API_H
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_constraint.h>
#include <mt_spm_internal.h>
#define SPM_RC_BITS_SET(dest, src) ({ (dest) |= (src); })
#define SPM_RC_BITS_CLR(dest, src) ({ (dest) &= (~src); })
int spm_rc_condition_modifier(unsigned int id, unsigned int act,
const void *val,
enum mt_spm_rm_rc_type dest_rc_id,
struct mt_spm_cond_tables * const tlb);
int spm_rc_constraint_status_get(unsigned int id, unsigned int type,
unsigned int act,
enum mt_spm_rm_rc_type dest_rc_id,
struct constraint_status * const src,
struct constraint_status * const dest);
int spm_rc_constraint_status_set(unsigned int id, unsigned int type,
unsigned int act,
enum mt_spm_rm_rc_type dest_rc_id,
struct constraint_status * const src,
struct constraint_status * const dest);
int spm_rc_constraint_valid_set(enum mt_spm_rm_rc_type id,
enum mt_spm_rm_rc_type dest_rc_id,
unsigned int valid,
struct constraint_status * const dest);
int spm_rc_constraint_valid_clr(enum mt_spm_rm_rc_type id,
enum mt_spm_rm_rc_type dest_rc_id,
unsigned int valid,
struct constraint_status * const dest);
#endif

397
plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c Normal file
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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#ifndef MTK_PLAT_CIRQ_UNSUPPORT
#include <mtk_cirq.h>
#endif
#include <drivers/spm/mt_spm_resource_req.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include "mt_spm_rc_api.h"
#include "mt_spm_rc_internal.h"
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#define CONSTRAINT_BUS26M_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
#define CONSTRAINT_BUS26M_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
#define CONSTRAINT_BUS26M_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
#define CONSTRAINT_BUS26M_RESOURCE_REQ (MT_SPM_26M)
#else
#define CONSTRAINT_BUS26M_RESOURCE_REQ (0)
#endif
static unsigned int bus26m_ext_opand;
static unsigned int bus26m_ext_opand2;
static struct mt_irqremain *refer2remain_irq;
static struct mt_spm_cond_tables cond_bus26m = {
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
0x27AF8000, /* INFRA0 */
0x22010876, /* INFRA1 */
0x86000650, /* INFRA2 */
0x30008020, /* INFRA3 */
0x80000000, /* INFRA4 */
0x01002A3B, /* PERI0 */
0x00090000, /* VPPSYS0_0 */
0x38FF3E69, /* VPPSYS0_1 */
0xF0081450, /* VPPSYS1_0 */
0x00003000, /* VPPSYS1_1 */
0x00000000, /* VDOSYS0_0 */
0x00000000, /* VDOSYS0_1 */
0x000001FF, /* VDOSYS1_0 */
0x000001E0, /* VDOSYS1_1 */
0x00FB0007, /* VDOSYS1_2 */
},
.table_pll = (PLL_BIT_UNIVPLL |
PLL_BIT_MFGPLL |
PLL_BIT_MSDCPLL |
PLL_BIT_TVDPLL1 |
PLL_BIT_TVDPLL2 |
PLL_BIT_MMPLL |
PLL_BIT_ETHPLL |
PLL_BIT_IMGPLL |
PLL_BIT_APLL1 |
PLL_BIT_APLL2 |
PLL_BIT_APLL3 |
PLL_BIT_APLL4 |
PLL_BIT_APLL5),
};
static struct mt_spm_cond_tables cond_bus26m_res = {
.table_cg = { 0U },
.table_pll = 0U,
};
static struct constraint_status status = {
.id = MT_RM_CONSTRAINT_ID_BUS26M,
.is_valid = (MT_SPM_RC_VALID_SW |
MT_SPM_RC_VALID_COND_CHECK |
MT_SPM_RC_VALID_COND_LATCH |
MT_SPM_RC_VALID_TRACE_TIME),
.is_cond_block = 0U,
.enter_cnt = 0U,
.all_pll_dump = 0U,
.cond_res = &cond_bus26m_res,
.residency = 0ULL,
};
#ifdef MTK_PLAT_CIRQ_UNSUPPORT
#define do_irqs_delivery()
#else
static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
unsigned int irq_index,
struct wake_status *wakeup)
{
if ((irqs == NULL) || (wakeup == NULL)) {
return;
}
INFO("[SPM] r12=0x%08x(0x%08x), flag=0x%08x 0x%08x 0x%08x, irq:%u(0x%08x) set pending\n",
wakeup->tr.comm.r12,
wakeup->md32pcm_wakeup_sta,
wakeup->tr.comm.debug_flag,
wakeup->tr.comm.b_sw_flag0,
wakeup->tr.comm.b_sw_flag1,
irqs->wakeupsrc[irq_index],
irqs->irqs[irq_index]);
}
static void do_irqs_delivery(void)
{
unsigned int idx;
struct wake_status *wakeup = NULL;
struct mt_irqremain *irqs = refer2remain_irq;
if (irqs == NULL) {
return;
}
if (spm_conservation_get_result(&wakeup) == 0) {
if (wakeup != NULL) {
for (idx = 0; idx < irqs->count; idx++) {
if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
((wakeup->tr.comm.raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
if ((irqs->wakeupsrc_cat[idx] &
MT_IRQ_REMAIN_CAT_LOG) != 0U) {
mt_spm_irq_remain_dump(irqs, idx, wakeup);
}
mt_irq_set_pending(irqs->irqs[idx]);
}
}
}
}
}
#endif
int spm_bus26m_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
{
unsigned int res_req = CONSTRAINT_BUS26M_RESOURCE_REQ;
if ((spm_lp == NULL) || (resource_req == NULL)) {
return -1;
}
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
*resource_req |= res_req;
return 0;
}
bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
{
return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
IS_MT_RM_RC_READY(status.is_valid) &&
(IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
static int update_rc_condition(const void *val)
{
const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
const struct mt_spm_cond_tables *tlb_check =
(const struct mt_spm_cond_tables *)&cond_bus26m;
if (tlb == NULL) {
return MT_RM_STATUS_BAD;
}
status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_bus26m_res : NULL);
status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_bus26m_res : NULL);
return MT_RM_STATUS_OK;
}
static void update_rc_remain_irqs(const void *val)
{
refer2remain_irq = (struct mt_irqremain *)val;
}
static void update_rc_fmaudio_adsp(int type, const void *val)
{
int *flag = (int *)val;
unsigned int ext_op = (type == PLAT_RC_IS_ADSP) ?
(MT_SPM_EX_OP_SET_IS_ADSP | MT_SPM_EX_OP_SET_SUSPEND_MODE) :
MT_SPM_EX_OP_SET_SUSPEND_MODE;
if (flag == NULL) {
return;
}
if (*flag != 0) {
SPM_RC_BITS_SET(bus26m_ext_opand, ext_op);
} else {
SPM_RC_BITS_CLR(bus26m_ext_opand, ext_op);
}
}
static void update_rc_usb_peri(const void *val)
{
int *flag = (int *)val;
if (flag == NULL) {
return;
}
if (*flag != 0) {
SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
} else {
SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_PERI_ON);
}
}
static void update_rc_usb_infra(const void *val)
{
int *flag = (int *)val;
if (flag == NULL) {
return;
}
if (*flag != 0) {
SPM_RC_BITS_SET(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
} else {
SPM_RC_BITS_CLR(bus26m_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
}
}
static void update_rc_status(const void *val)
{
const struct rc_common_state *st;
st = (const struct rc_common_state *)val;
if (st == NULL) {
return;
}
if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
struct mt_spm_cond_tables * const tlb = &cond_bus26m;
spm_rc_condition_modifier(st->id, st->act, st->value,
MT_RM_CONSTRAINT_ID_BUS26M, tlb);
} else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
(st->type == CONSTRAINT_RESIDNECY)) {
spm_rc_constraint_status_set(st->id, st->type, st->act,
MT_RM_CONSTRAINT_ID_BUS26M,
(struct constraint_status * const)st->value,
(struct constraint_status * const)&status);
} else {
INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
}
}
int spm_update_rc_bus26m(int state_id, int type, const void *val)
{
int res = MT_RM_STATUS_OK;
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
res = update_rc_condition(val);
break;
case PLAT_RC_UPDATE_REMAIN_IRQS:
update_rc_remain_irqs(val);
break;
case PLAT_RC_IS_FMAUDIO:
case PLAT_RC_IS_ADSP:
update_rc_fmaudio_adsp(type, val);
break;
case PLAT_RC_IS_USB_PERI:
update_rc_usb_peri(val);
break;
case PLAT_RC_IS_USB_INFRA:
update_rc_usb_infra(val);
break;
case PLAT_RC_STATUS:
update_rc_status(val);
break;
default:
INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
break;
}
return res;
}
unsigned int spm_allow_rc_bus26m(int state_id)
{
return CONSTRAINT_BUS26M_ALLOW;
}
int spm_run_rc_bus26m(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
(IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
#endif
if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(MT_SPM_EX_OP_CLR_26M_RECORD |
MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_HW_S1_DETECT |
bus26m_ext_opand |
bus26m_ext_opand2),
CONSTRAINT_BUS26M_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
}
return MT_RM_STATUS_OK;
}
int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0);
#endif
if (status.is_valid & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id,
(bus26m_ext_opand | bus26m_ext_opand2 |
MT_SPM_EX_OP_SET_WDT | ext_op),
NULL);
bus26m_ext_opand = 0;
} else {
struct wake_status *waken = NULL;
if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
ext_op |= MT_SPM_EX_OP_TRACE_LP;
}
mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
status.enter_cnt++;
if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
}
}
do_irqs_delivery();
return MT_RM_STATUS_OK;
}
int spm_get_status_rc_bus26m(unsigned int type, void *priv)
{
int ret = MT_RM_STATUS_OK;
if (type == PLAT_RC_STATUS) {
int res = 0;
struct rc_common_state *st = (struct rc_common_state *)priv;
if (st == NULL) {
return MT_RM_STATUS_BAD;
}
res = spm_rc_constraint_status_get(st->id, st->type,
st->act, MT_RM_CONSTRAINT_ID_BUS26M,
(struct constraint_status * const)&status,
(struct constraint_status * const)st->value);
if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
ret = MT_RM_STATUS_STOP;
}
}
return ret;
}

191
plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_cpu_buck_ldo.c Normal file
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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/spm/mt_spm_resource_req.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lpm_smc.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include "mt_spm_rc_api.h"
#include "mt_spm_rc_internal.h"
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#define CONSTRAINT_CPU_BUCK_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 (0)
#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ (MT_SPM_DRAM_S1 | \
MT_SPM_DRAM_S0 | \
MT_SPM_SYSPLL | \
MT_SPM_INFRA | \
MT_SPM_26M | \
MT_SPM_XO_FPM)
static unsigned int cpubuckldo_status = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_TRACE_TIME);
static unsigned int cpubuckldo_enter_cnt;
int spm_cpu_bcuk_ldo_conduct(int state_id,
struct spm_lp_scen *spm_lp,
unsigned int *resource_req)
{
unsigned int res_req = CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
if ((spm_lp == NULL) || (resource_req == NULL)) {
return -1;
}
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
*resource_req |= res_req;
return 0;
}
bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
{
return IS_MT_RM_RC_READY(cpubuckldo_status);
}
static void update_rc_status(const void *val)
{
const struct rc_common_state *st = (const struct rc_common_state *)val;
if (st == NULL) {
return;
}
if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) {
if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
(st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
struct constraint_status *con = (struct constraint_status *)st->value;
if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) {
SPM_RC_BITS_CLR(cpubuckldo_status, con->is_valid);
} else {
SPM_RC_BITS_SET(cpubuckldo_status, con->is_valid);
}
}
}
}
int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val)
{
if (type == PLAT_RC_STATUS) {
update_rc_status(val);
}
return MT_RM_STATUS_OK;
}
unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
{
return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
}
int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
{
(void)cpu;
unsigned int ext_op = 0U;
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
(IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : (0U)));
#endif
if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(MT_SPM_EX_OP_CLR_26M_RECORD |
MT_SPM_EX_OP_SET_SUSPEND_MODE |
MT_SPM_EX_OP_SET_WDT),
CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, ext_op, spm_cpu_bcuk_ldo_conduct);
}
cpubuckldo_enter_cnt++;
return 0;
}
int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
{
(void)cpu;
unsigned int ext_op = 0U;
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
#endif
if (cpubuckldo_status & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
} else {
mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
}
return 0;
}
int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv)
{
int ret = MT_RM_STATUS_OK;
if (type != PLAT_RC_STATUS) {
return ret;
}
struct rc_common_state *st = (struct rc_common_state *)priv;
if (st == NULL) {
return MT_RM_STATUS_BAD;
}
if ((st->id == MT_RM_CONSTRAINT_ID_ALL) ||
(st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) {
struct constraint_status *dest;
dest = (struct constraint_status *)st->value;
do {
if (dest == NULL) {
break;
}
if (st->type == CONSTRAINT_GET_VALID) {
dest->is_valid = cpubuckldo_status;
} else if (st->type == CONSTRAINT_COND_BLOCK) {
dest->is_cond_block = 0;
} else if (st->type == CONSTRAINT_GET_ENTER_CNT) {
if (st->id == MT_RM_CONSTRAINT_ID_ALL) {
dest->enter_cnt += cpubuckldo_enter_cnt;
} else {
dest->enter_cnt = cpubuckldo_enter_cnt;
}
} else {
break;
}
if (st->id != MT_RM_CONSTRAINT_ID_ALL) {
ret = MT_RM_STATUS_STOP;
}
} while (0);
}
return ret;
}

317
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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/spm/mt_spm_resource_req.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_api.h>
#include <lpm/mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include "mt_spm_rc_api.h"
#include "mt_spm_rc_internal.h"
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#define CONSTRAINT_DRAM_ALLOW (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
#define CONSTRAINT_DRAM_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
#define CONSTRAINT_DRAM_PCM_FLAG1 (0)
#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
static struct mt_spm_cond_tables cond_dram = {
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
0x27AF8000, /* INFRA0 */
0x20010876, /* INFRA1 */
0x86000640, /* INFRA2 */
0x00000000, /* INFRA3 */
0x80000000, /* INFRA4 */
0x01002A00, /* PERI0 */
0x00080000, /* VPPSYS0_0 */
0x38803000, /* VPPSYS0_1 */
0x00081450, /* VPPSYS1_0 */
0x00003000, /* VPPSYS1_1 */
0x00000000, /* VDOSYS0_0 */
0x00000000, /* VDOSYS0_1 */
0x000001F8, /* VDOSYS1_0 */
0x000001E0, /* VDOSYS1_1 */
0x00FB0007, /* VDOSYS1_2 */
},
.table_pll = 0U,
};
static struct mt_spm_cond_tables cond_dram_res = {
.table_cg = { 0U },
.table_pll = 0U,
};
static struct constraint_status status = {
.id = MT_RM_CONSTRAINT_ID_DRAM,
.is_valid = (MT_SPM_RC_VALID_SW |
MT_SPM_RC_VALID_COND_CHECK |
MT_SPM_RC_VALID_COND_LATCH |
MT_SPM_RC_VALID_XSOC_BBLPM |
MT_SPM_RC_VALID_TRACE_TIME),
.is_cond_block = 0U,
.enter_cnt = 0U,
.cond_res = &cond_dram_res,
.residency = 0ULL,
};
static unsigned short ext_status_dram;
int spm_dram_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
{
unsigned int res_req = CONSTRAINT_DRAM_RESOURCE_REQ;
if ((spm_lp == NULL) || (resource_req == NULL)) {
return -1;
}
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
*resource_req |= res_req;
return 0;
}
bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
{
return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK)) &&
IS_MT_RM_RC_READY(status.is_valid) &&
(IS_PLAT_SUSPEND_ID(state_id) ||
(state_id == MT_PLAT_PWR_STATE_SYSTEM_MEM) ||
(state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
(state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
static int update_rc_condition(const void *val)
{
const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
if (tlb == NULL) {
return MT_RM_STATUS_BAD;
}
status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_dram_res : NULL);
return MT_RM_STATUS_OK;
}
static void update_rc_clkbuf_status(const void *val)
{
unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
if (is_flight != 0U) {
spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_DRAM,
MT_SPM_RC_VALID_FLIGHTMODE,
(struct constraint_status * const)&status);
} else {
spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_DRAM,
MT_SPM_RC_VALID_FLIGHTMODE,
(struct constraint_status * const)&status);
}
}
static void update_rc_ufs_status(const void *val)
{
unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
if (is_ufs_h8 != 0U) {
spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_DRAM,
MT_SPM_RC_VALID_UFS_H8,
(struct constraint_status * const)&status);
} else {
spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_DRAM,
MT_RM_CONSTRAINT_ID_DRAM,
MT_SPM_RC_VALID_UFS_H8,
(struct constraint_status * const)&status);
}
}
static void update_rc_status(const void *val)
{
const struct rc_common_state *st;
st = (const struct rc_common_state *)val;
if (st == NULL) {
return;
}
if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
struct mt_spm_cond_tables * const tlb = &cond_dram;
spm_rc_condition_modifier(st->id, st->act, st->value,
MT_RM_CONSTRAINT_ID_DRAM, tlb);
} else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
(st->type == CONSTRAINT_RESIDNECY)) {
spm_rc_constraint_status_set(st->id, st->type, st->act,
MT_RM_CONSTRAINT_ID_DRAM,
(struct constraint_status * const)st->value,
(struct constraint_status * const)&status);
} else {
INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
}
}
int spm_update_rc_dram(int state_id, int type, const void *val)
{
int res = MT_RM_STATUS_OK;
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
res = update_rc_condition(val);
break;
case PLAT_RC_CLKBUF_STATUS:
update_rc_clkbuf_status(val);
break;
case PLAT_RC_UFS_STATUS:
update_rc_ufs_status(val);
break;
case PLAT_RC_STATUS:
update_rc_status(val);
break;
default:
INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
break;
}
return res;
}
unsigned int spm_allow_rc_dram(int state_id)
{
return CONSTRAINT_DRAM_ALLOW;
}
int spm_run_rc_dram(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_DRAM_ALLOW;
ext_status_dram = status.is_valid;
if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
(MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
#else
(void)allows;
#endif
if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(MT_SPM_EX_OP_CLR_26M_RECORD |
MT_SPM_EX_OP_SET_WDT |
MT_SPM_EX_OP_SET_SUSPEND_MODE |
MT_SPM_EX_OP_HW_S1_DETECT),
CONSTRAINT_DRAM_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
}
return 0;
}
int spm_reset_rc_dram(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_DRAM_ALLOW;
if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_dram)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
#else
(void)allows;
#endif
if (ext_status_dram & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id,
(MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
NULL);
} else {
struct wake_status *waken = NULL;
if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
ext_op |= MT_SPM_EX_OP_TRACE_LP;
}
mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
status.enter_cnt++;
if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
}
}
return 0;
}
int spm_get_status_rc_dram(unsigned int type, void *priv)
{
int ret = MT_RM_STATUS_OK;
if (type == PLAT_RC_STATUS) {
int res = 0;
struct rc_common_state *st = (struct rc_common_state *)priv;
if (st == NULL) {
return MT_RM_STATUS_BAD;
}
res = spm_rc_constraint_status_get(st->id, st->type,
st->act, MT_RM_CONSTRAINT_ID_DRAM,
(struct constraint_status * const)&status,
(struct constraint_status * const)st->value);
if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
ret = MT_RM_STATUS_STOP;
}
}
return ret;
}

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plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_internal.h Normal file
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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_RC_INTERNAL_H
#define MT_SPM_RC_INTERNAL_H
#ifdef MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT
#define SPM_FLAG_SRAM_SLEEP_CTRL (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
#else
#define SPM_FLAG_SRAM_SLEEP_CTRL (0)
#define SPM_SRAM_SLEEP_RC_RES_RESTRICT (0)
#endif
#define SPM_RC_UPDATE_COND_ID_MASK (0xffff)
#define SPM_RC_UPDATE_COND_RC_ID_MASK (0xffff)
#define SPM_RC_UPDATE_COND_RC_ID_SHIFT (16)
#define SPM_RC_UPDATE_COND_RC_ID_GET(val) \
((val >> SPM_RC_UPDATE_COND_RC_ID_SHIFT) & SPM_RC_UPDATE_COND_RC_ID_MASK)
#define SPM_RC_UPDATE_COND_ID_GET(val) (val & SPM_RC_UPDATE_COND_ID_MASK)
/* cpu buck/ldo constraint function */
bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
int spm_update_rc_cpu_buck_ldo(int state_id, int type, const void *val);
unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
int spm_get_status_rc_cpu_buck_ldo(unsigned int type, void *priv);
/* spm resource dram constraint function */
bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
int spm_update_rc_dram(int state_id, int type, const void *val);
unsigned int spm_allow_rc_dram(int state_id);
int spm_run_rc_dram(unsigned int cpu, int state_id);
int spm_reset_rc_dram(unsigned int cpu, int state_id);
int spm_get_status_rc_dram(unsigned int type, void *priv);
/* spm resource syspll constraint function */
bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
int spm_update_rc_syspll(int state_id, int type, const void *val);
unsigned int spm_allow_rc_syspll(int state_id);
int spm_run_rc_syspll(unsigned int cpu, int state_id);
int spm_reset_rc_syspll(unsigned int cpu, int state_id);
int spm_get_status_rc_syspll(unsigned int type, void *priv);
/* spm resource bus26m constraint function */
bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
int spm_update_rc_bus26m(int state_id, int type, const void *val);
unsigned int spm_allow_rc_bus26m(int state_id);
int spm_run_rc_bus26m(unsigned int cpu, int state_id);
int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
int spm_get_status_rc_bus26m(unsigned int type, void *priv);
#endif

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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
#include <drivers/spm/mt_spm_resource_req.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_api.h>
#include <lpm/mt_lp_rm.h>
#include <mt_spm.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_notifier.h>
#include "mt_spm_rc_api.h"
#include "mt_spm_rc_internal.h"
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#define CONSTRAINT_SYSPLL_ALLOW (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
#define CONSTRAINT_SYSPLL_PCM_FLAG (SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_SRAM_SLEEP_CTRL | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_ENABLE_6315_CTRL | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_USE_SRCCLKENO2)
#define CONSTRAINT_SYSPLL_PCM_FLAG1 (0)
/* If sspm sram won't enter sleep voltage then vcore couldn't enter low power mode */
#if defined(MTK_PLAT_SPM_SRAM_SLP_UNSUPPORT) && SPM_SRAM_SLEEP_RC_RES_RESTRICT
#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
#else
#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
#endif
static unsigned int syspll_ext_opand2;
static unsigned short ext_status_syspll;
static struct mt_spm_cond_tables cond_syspll = {
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
0x27AF8000, /* INFRA0 */
0x20010876, /* INFRA1 */
0x86000640, /* INFRA2 */
0x30008020, /* INFRA3 */
0x80000000, /* INFRA4 */
0x01002A0B, /* PERI0 */
0x00090000, /* VPPSYS0_0 */
0x38FF3E69, /* VPPSYS0_1 */
0xF0081450, /* VPPSYS1_0 */
0x00003000, /* VPPSYS1_1 */
0x00000000, /* VDOSYS0_0 */
0x00000000, /* VDOSYS0_1 */
0x000001FF, /* VDOSYS1_0 */
0x008001E0, /* VDOSYS1_1 */
0x00FB0007, /* VDOSYS1_2 */
},
.table_pll = 0U,
};
static struct mt_spm_cond_tables cond_syspll_res = {
.table_cg = { 0U },
.table_pll = 0U,
};
static struct constraint_status status = {
.id = MT_RM_CONSTRAINT_ID_SYSPLL,
.is_valid = (MT_SPM_RC_VALID_SW |
MT_SPM_RC_VALID_COND_CHECK |
MT_SPM_RC_VALID_COND_LATCH |
MT_SPM_RC_VALID_XSOC_BBLPM |
MT_SPM_RC_VALID_TRACE_TIME),
.is_cond_block = 0U,
.enter_cnt = 0U,
.cond_res = &cond_syspll_res,
.residency = 0ULL,
};
int spm_syspll_conduct(int state_id, struct spm_lp_scen *spm_lp, unsigned int *resource_req)
{
unsigned int res_req = CONSTRAINT_SYSPLL_RESOURCE_REQ;
if ((spm_lp == NULL) || (resource_req == NULL)) {
return -1;
}
spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
*resource_req |= res_req;
return 0;
}
bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
{
return (!(status.is_cond_block && (status.is_valid & MT_SPM_RC_VALID_COND_CHECK) > 0) &&
IS_MT_RM_RC_READY(status.is_valid) &&
(IS_PLAT_SUSPEND_ID(state_id) ||
(state_id == MT_PLAT_PWR_STATE_SYSTEM_PLL) ||
(state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
static int update_rc_condition(const void *val)
{
int res = MT_RM_STATUS_OK;
const struct mt_spm_cond_tables * const tlb =
(const struct mt_spm_cond_tables * const)val;
const struct mt_spm_cond_tables *tlb_check =
(const struct mt_spm_cond_tables *)&cond_syspll;
if (tlb == NULL) {
return MT_RM_STATUS_BAD;
}
status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_syspll_res : NULL);
return res;
}
static void update_rc_clkbuf_status(const void *val)
{
unsigned int is_flight = (val) ? !!(*((unsigned int *)val) == FLIGHT_MODE_ON) : 0;
if (is_flight != 0U) {
spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_SPM_RC_VALID_FLIGHTMODE,
(struct constraint_status * const)&status);
} else {
spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_SPM_RC_VALID_FLIGHTMODE,
(struct constraint_status * const)&status);
}
}
static void update_rc_ufs_status(const void *val)
{
unsigned int is_ufs_h8 = (val) ? !!(*((unsigned int *)val) == UFS_REF_CLK_OFF) : 0;
if (is_ufs_h8 != 0U) {
spm_rc_constraint_valid_set(MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_SPM_RC_VALID_UFS_H8,
(struct constraint_status * const)&status);
} else {
spm_rc_constraint_valid_clr(MT_RM_CONSTRAINT_ID_SYSPLL,
MT_RM_CONSTRAINT_ID_SYSPLL,
MT_SPM_RC_VALID_UFS_H8,
(struct constraint_status * const)&status);
}
}
static void update_rc_usb_peri(const void *val)
{
int *flag = (int *)val;
if (flag == NULL) {
return;
}
if (*flag != 0) {
SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
} else {
SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_PERI_ON);
}
}
static void update_rc_usb_infra(const void *val)
{
int *flag = (int *)val;
if (flag == NULL) {
return;
}
if (*flag != 0) {
SPM_RC_BITS_SET(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
} else {
SPM_RC_BITS_CLR(syspll_ext_opand2, MT_SPM_EX_OP_INFRA_ON);
}
}
static void update_rc_status(const void *val)
{
const struct rc_common_state *st;
st = (const struct rc_common_state *)val;
if (st == NULL) {
return;
}
if (st->type == CONSTRAINT_UPDATE_COND_CHECK) {
struct mt_spm_cond_tables * const tlb = &cond_syspll;
spm_rc_condition_modifier(st->id, st->act, st->value,
MT_RM_CONSTRAINT_ID_SYSPLL, tlb);
} else if ((st->type == CONSTRAINT_UPDATE_VALID) ||
(st->type == CONSTRAINT_RESIDNECY)) {
spm_rc_constraint_status_set(st->id, st->type, st->act,
MT_RM_CONSTRAINT_ID_SYSPLL,
(struct constraint_status * const)st->value,
(struct constraint_status * const)&status);
} else {
INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type);
}
}
int spm_update_rc_syspll(int state_id, int type, const void *val)
{
int res = MT_RM_STATUS_OK;
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
res = update_rc_condition(val);
break;
case PLAT_RC_CLKBUF_STATUS:
update_rc_clkbuf_status(val);
break;
case PLAT_RC_UFS_STATUS:
update_rc_ufs_status(val);
break;
case PLAT_RC_IS_USB_PERI:
update_rc_usb_peri(val);
break;
case PLAT_RC_IS_USB_INFRA:
update_rc_usb_infra(val);
break;
case PLAT_RC_STATUS:
update_rc_status(val);
break;
default:
INFO("[%s:%d] - Do nothing for type: %d\n", __func__, __LINE__, type);
break;
}
return res;
}
unsigned int spm_allow_rc_syspll(int state_id)
{
return CONSTRAINT_SYSPLL_ALLOW;
}
int spm_run_rc_syspll(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
ext_status_syspll = status.is_valid;
if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0));
#else
(void)allows;
#endif
if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_enter(state_id,
(syspll_ext_opand2 | MT_SPM_EX_OP_CLR_26M_RECORD |
MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT |
MT_SPM_EX_OP_SET_SUSPEND_MODE),
CONSTRAINT_SYSPLL_RESOURCE_REQ);
} else {
mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
}
return 0;
}
int spm_reset_rc_syspll(unsigned int cpu, int state_id)
{
unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
if (IS_MT_SPM_RC_BBLPM_MODE(ext_status_syspll)) {
#ifdef MT_SPM_USING_SRCLKEN_RC
ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
#else
allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
#endif
}
#ifndef MTK_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
#else
(void)allows;
#endif
if (ext_status_syspll & MT_SPM_RC_VALID_TRACE_TIME) {
ext_op |= MT_SPM_EX_OP_TRACE_TIMESTAMP_EN;
}
if (IS_PLAT_SUSPEND_ID(state_id)) {
mt_spm_suspend_resume(state_id,
(syspll_ext_opand2 | MT_SPM_EX_OP_SET_SUSPEND_MODE |
MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
NULL);
} else {
struct wake_status *waken = NULL;
if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_TRACE_EVENT)) {
ext_op |= MT_SPM_EX_OP_TRACE_LP;
}
mt_spm_idle_generic_resume(state_id, ext_op, &waken, NULL);
status.enter_cnt++;
if (spm_unlikely(status.is_valid & MT_SPM_RC_VALID_RESIDNECY)) {
status.residency += (waken != NULL) ? waken->tr.comm.timer_out : 0;
}
}
return 0;
}
int spm_get_status_rc_syspll(unsigned int type, void *priv)
{
int ret = MT_RM_STATUS_OK;
if (type == PLAT_RC_STATUS) {
int res = 0;
struct rc_common_state *st = (struct rc_common_state *)priv;
if (st == NULL) {
return MT_RM_STATUS_BAD;
}
res = spm_rc_constraint_status_get(st->id, st->type, st->act,
MT_RM_CONSTRAINT_ID_SYSPLL,
(struct constraint_status * const)&status,
(struct constraint_status * const)st->value);
if ((res == 0) && (st->id != MT_RM_CONSTRAINT_ID_ALL)) {
ret = MT_RM_STATUS_STOP;
}
}
return ret;
}

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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdbool.h>
#include <lib/mmio.h>
#include <lib/pm/mtk_pm.h>
#include <mt_spm_cond.h>
#include <mt_spm_conservation.h>
#include <mt_spm_constraint.h>
#include <platform_def.h>
#define TOPCKGEB_BASE (IO_PHYS)
#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEB_BASE + ofs)
#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
#define MT_LP_TZ_VPPSYS0_REG(ofs) (VPPSYS0_BASE + ofs)
#define MT_LP_TZ_VPPSYS1_REG(ofs) (VPPSYS1_BASE + ofs)
#define MT_LP_TZ_VDOSYS0_REG(ofs) (VDOSYS0_BASE + ofs)
#define MT_LP_TZ_VDOSYS1_REG(ofs) (VDOSYS1_BASE + ofs)
#define MT_LP_TZ_PERI_AO_REG(ofs) (PERICFG_AO_BASE + ofs)
#undef SPM_PWR_STATUS
#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
#define SPM_CPU_PWR_STATUS MT_LP_TZ_SPM_REG(0x0174)
#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0090)
#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0094)
#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00E8)
#define TOP_SW_I2C_CG MT_LP_TZ_TOPCK_REG(0x00A4)
#define PERI_SW_CG0 MT_LP_TZ_PERI_AO_REG(0x0018)
#define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020)
#define VPPSYS0_SW_CG1 MT_LP_TZ_VPPSYS0_REG(0x002C)
#define VPPSYS0_SW_CG2 MT_LP_TZ_VPPSYS0_REG(0x0038)
#define VPPSYS1_SW_CG0 MT_LP_TZ_VPPSYS1_REG(0x0100)
#define VPPSYS1_SW_CG1 MT_LP_TZ_VPPSYS1_REG(0x0110)
#define VDOSYS0_SW_CG0 MT_LP_TZ_VDOSYS0_REG(0x0100)
#define VDOSYS0_SW_CG1 MT_LP_TZ_VDOSYS0_REG(0x0110)
#define VDOSYS1_SW_CG0 MT_LP_TZ_VDOSYS1_REG(0x0100)
#define VDOSYS1_SW_CG1 MT_LP_TZ_VDOSYS1_REG(0x0120)
#define VDOSYS1_SW_CG2 MT_LP_TZ_VDOSYS1_REG(0x0130)
#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x2c + id * 0xc)
enum {
/* CLK_CFG_0 1000_002c */
CLKMUX_VPP = 0,
NF_CLKMUX,
};
#define CLK_CHECK BIT(31)
static bool check_clkmux_pdn(unsigned int clkmux_id)
{
unsigned int reg, val, idx;
bool ret = false;
if ((clkmux_id & CLK_CHECK) != 0U) {
clkmux_id = (clkmux_id & ~CLK_CHECK);
reg = clkmux_id / 4U;
val = mmio_read_32(CLK_CFG(reg));
idx = clkmux_id % 4U;
ret = (((val >> (idx * 8U)) & 0x80) != 0U);
}
return ret;
}
static struct mt_spm_cond_tables spm_cond_t;
/* local definitions */
struct idle_cond_info {
/* check SPM_PWR_STATUS for bit definition */
unsigned int subsys_mask;
/* cg address */
uintptr_t addr;
/* bitflip value from *addr ? */
bool bBitflip;
/* check clkmux if bit 31 = 1, id is bit[30:0] */
unsigned int clkmux_id;
};
#define IDLE_CG(mask, addr, bitflip, clkmux) {mask, (uintptr_t)addr, bitflip, clkmux}
static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0),
IDLE_CG(0xffffffff, SPM_CPU_PWR_STATUS, false, 0),
IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0),
IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0),
IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0),
IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0),
IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0),
IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0),
IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK | CLKMUX_VPP)),
IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK | CLKMUX_VPP)),
};
/* check pll idle condition */
#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x340)
#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x544)
#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x504)
#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x514)
#define PLL_TVDPLL1 MT_LP_TZ_APMIXEDSYS(0x524)
#define PLL_TVDPLL2 MT_LP_TZ_APMIXEDSYS(0x534)
#define PLL_ETHPLL MT_LP_TZ_APMIXEDSYS(0x44c)
#define PLL_IMGPLL MT_LP_TZ_APMIXEDSYS(0x554)
#define PLL_APLL1 MT_LP_TZ_APMIXEDSYS(0x304)
#define PLL_APLL2 MT_LP_TZ_APMIXEDSYS(0x318)
#define PLL_APLL3 MT_LP_TZ_APMIXEDSYS(0x32c)
#define PLL_APLL4 MT_LP_TZ_APMIXEDSYS(0x404)
#define PLL_APLL5 MT_LP_TZ_APMIXEDSYS(0x418)
unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res)
{
unsigned int b_res = 0U;
unsigned int i;
if ((src == NULL) || (dest == NULL)) {
return SPM_COND_CHECK_FAIL;
}
for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
if (res != NULL) {
res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
if ((res->table_cg[i]) != 0U) {
b_res |= BIT(i);
}
} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
b_res |= BIT(i);
break;
}
}
if (res != NULL) {
res->table_pll = (src->table_pll & dest->table_pll);
if ((res->table_pll) != 0U) {
b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
SPM_COND_CHECK_BLOCKED_PLL;
}
} else if ((src->table_pll & dest->table_pll) != 0U) {
b_res |= SPM_COND_CHECK_BLOCKED_PLL;
}
return b_res;
}
unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res)
{
unsigned int b_res = 0U;
if (res != NULL) {
res->table_all_pll = src->table_all_pll;
if ((res->table_all_pll) != 0U) {
b_res |= (res->table_all_pll << SPM_COND_BLOCKED_PLL_IDX) |
SPM_COND_CHECK_BLOCKED_PLL;
}
} else if ((src->table_pll & dest->table_pll) != 0U) {
b_res |= SPM_COND_CHECK_BLOCKED_PLL;
}
return b_res;
}
#define IS_MT_SPM_PWR_OFF(mask) \
(!(mmio_read_32(SPM_PWR_STATUS) & mask) && \
!(mmio_read_32(SPM_PWR_STATUS_2ND) & mask))
int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv)
{
static const struct {
uintptr_t en_reg;
uint32_t pll_b;
} plls[] = {
{ PLL_MFGPLL, PLL_BIT_MFGPLL },
{ PLL_MMPLL, PLL_BIT_MMPLL },
{ PLL_UNIVPLL, PLL_BIT_UNIVPLL },
{ PLL_MSDCPLL, PLL_BIT_MSDCPLL },
{ PLL_TVDPLL1, PLL_BIT_TVDPLL1 },
{ PLL_TVDPLL2, PLL_BIT_TVDPLL2 },
{ PLL_ETHPLL, PLL_BIT_ETHPLL },
{ PLL_IMGPLL, PLL_BIT_IMGPLL },
{ PLL_APLL1, PLL_BIT_APLL1 },
{ PLL_APLL2, PLL_BIT_APLL2 },
{ PLL_APLL3, PLL_BIT_APLL3 },
{ PLL_APLL4, PLL_BIT_APLL4 },
{ PLL_APLL5, PLL_BIT_APLL5 },
};
int i, res;
struct mt_resource_constraint *const *_con;
/* read all cg state */
for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
spm_cond_t.table_cg[i] = 0U;
/* check mtcmos, if off set idle_value and clk to 0 disable */
if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
continue;
}
/* check clkmux */
if (check_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
continue;
}
spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
~mmio_read_32(idle_cg_info[i].addr) :
mmio_read_32(idle_cg_info[i].addr);
}
spm_cond_t.table_pll = 0U;
for (i = 0; i < ARRAY_SIZE(plls); i++) {
if ((mmio_read_32(plls[i].en_reg) & BIT(9)) != 0U) {
spm_cond_t.table_pll |= plls[i].pll_b;
}
}
spm_cond_t.priv = priv;
for (_con = con; *_con != NULL ; _con++) {
if ((*_con)->update == NULL) {
continue;
}
res = (*_con)->update(stateid, PLAT_RC_UPDATE_CONDITION,
(void const *)&spm_cond_t);
if (res != MT_RM_STATUS_OK) {
break;
}
}
return 0;
}

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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_COND_H
#define MT_SPM_COND_H
#include <lpm/mt_lp_rm.h>
enum plat_spm_cond {
PLAT_SPM_COND_MTCMOS1 = 0,
PLAT_SPM_COND_MTCMOS2,
PLAT_SPM_COND_CG_INFRA_0,
PLAT_SPM_COND_CG_INFRA_1,
PLAT_SPM_COND_CG_INFRA_2,
PLAT_SPM_COND_CG_INFRA_3,
PLAT_SPM_COND_CG_INFRA_4,
PLAT_SPM_COND_CG_PERI_0,
PLAT_SPM_COND_CG_VPPSYS0_0,
PLAT_SPM_COND_CG_VPPSYS0_1,
PLAT_SPM_COND_CG_VPPSYS1_0,
PLAT_SPM_COND_CG_VPPSYS1_1,
PLAT_SPM_COND_CG_VDOSYS0_0,
PLAT_SPM_COND_CG_VDOSYS0_1,
PLAT_SPM_COND_CG_VDOSYS1_0,
PLAT_SPM_COND_CG_VDOSYS1_1,
PLAT_SPM_COND_CG_VDOSYS1_2,
PLAT_SPM_COND_MAX,
};
/* For PLL id >= PLAT_SPM_COND_PLL_MAX is not checked in idle condition */
enum plat_spm_cond_pll {
PLAT_SPM_COND_PLL_UNIVPLL = 0,
PLAT_SPM_COND_PLL_MFGPLL,
PLAT_SPM_COND_PLL_MSDCPLL,
PLAT_SPM_COND_PLL_TVDPLL1,
PLAT_SPM_COND_PLL_TVDPLL2,
PLAT_SPM_COND_PLL_MMPLL,
PLAT_SPM_COND_PLL_ETHPLL,
PLAT_SPM_COND_PLL_IMGPLL,
PLAT_SPM_COND_PLL_APLL1,
PLAT_SPM_COND_PLL_APLL2,
PLAT_SPM_COND_PLL_APLL3,
PLAT_SPM_COND_PLL_APLL4,
PLAT_SPM_COND_PLL_APLL5,
PLAT_SPM_COND_PLL_MAX,
};
#define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL)
#define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL)
#define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL)
#define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL)
#define PLL_BIT_TVDPLL1 BIT(PLAT_SPM_COND_PLL_TVDPLL1)
#define PLL_BIT_TVDPLL2 BIT(PLAT_SPM_COND_PLL_TVDPLL2)
#define PLL_BIT_ETHPLL BIT(PLAT_SPM_COND_PLL_ETHPLL)
#define PLL_BIT_IMGPLL BIT(PLAT_SPM_COND_PLL_IMGPLL)
#define PLL_BIT_APLL1 BIT(PLAT_SPM_COND_PLL_APLL1)
#define PLL_BIT_APLL2 BIT(PLAT_SPM_COND_PLL_APLL2)
#define PLL_BIT_APLL3 BIT(PLAT_SPM_COND_PLL_APLL3)
#define PLL_BIT_APLL4 BIT(PLAT_SPM_COND_PLL_APLL4)
#define PLL_BIT_APLL5 BIT(PLAT_SPM_COND_PLL_APLL5)
/*
* Definition about SPM_COND_CHECK_BLOCKED
* bit[00:16]: cg blocking index
* bit[17:29]: pll blocking index
* bit[30]: pll blocking information
* bit[31]: idle condition check fail
*/
#define SPM_COND_BLOCKED_CG_IDX (0)
#define SPM_COND_BLOCKED_PLL_IDX (17)
#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
#define SPM_COND_CHECK_FAIL BIT(31)
struct mt_spm_cond_tables {
unsigned int table_cg[PLAT_SPM_COND_MAX];
unsigned int table_pll;
unsigned int table_all_pll;
void *priv;
};
unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv);
#endif

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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
#include <stdio.h>
#include <string.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <drivers/spm/mt_spm_resource_req.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_api.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_idle.h>
#include <mt_spm_internal.h>
#include <mt_spm_reg.h>
#define SPM_BYPASS_SYSPWREQ_GENERIC (1)
#define __WAKE_SRC_FOR_IDLE_COMMON__ ( \
(R12_PCM_TIMER) | \
(R12_KP_IRQ_B) | \
(R12_APWDT_EVENT_B) | \
(R12_APXGPT1_EVENT_B) | \
(R12_MSDC_WAKEUP_B) | \
(R12_EINT_EVENT_B) | \
(R12_SBD_INTR_WAKEUP_B) | \
(R12_SSPM2SPM_WAKEUP_B) | \
(R12_SCP2SPM_WAKEUP_B) | \
(R12_ADSP2SPM_WAKEUP_B) | \
(R12_USBX_CDSC_B) | \
(R12_USBX_POWERDWN_B) | \
(R12_SYS_TIMER_EVENT_B) | \
(R12_EINT_EVENT_SECURE_B) | \
(R12_ECE_INT_HDMI_B) | \
(R12_AFE_IRQ_MCU_B) | \
(R12_SYS_CIRQ_IRQ_B) | \
(R12_PCIE_WAKEUPEVENT_B) | \
(R12_SPM_CPU_WAKEUPEVENT_B) | \
(R12_APUSYS_WAKE_HOST_B))
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
#else
#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__ | R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl idle_spm_pwr = {
.wake_src = WAKE_SRC_FOR_IDLE,
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 0,
/* [3] */
.reg_spm_infra_req = 0,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] */
.reg_spm_ddr_en_req = 0,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 1,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 1,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 1,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 1,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* [30] */
.reg_cam_ddren_req_mask_b = 1,
/* [31] */
.reg_img_ddren_req_mask_b = 1,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 1,
/* [16] */
.reg_ufs_infra_req_mask_b = 1,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 1,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 1,
/* [19] */
.reg_ufs_ddr_en_mask_b = 1,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 3,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 3,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xC1282203,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
};
struct spm_lp_scen idle_spm_lp = {
.pwrctrl = &idle_spm_pwr,
};
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn)
{
int ret = 0;
unsigned int src_req = 0U;
if (fn != NULL) {
fn(state_id, &idle_spm_lp, &src_req);
}
ret = spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
if (ret == 0) {
struct mt_lp_publish_event event = {
.id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
.val.u32 = 0U,
};
MT_LP_PUBLISH_EVENT(&event);
}
return ret;
}
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status,
spm_idle_conduct_restore fn)
{
struct mt_lp_publish_event event = {
.id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
.val.u32 = 0U,
};
ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
if (spm_unlikely(fn)) {
fn(state_id, &idle_spm_lp, *status);
}
MT_LP_PUBLISH_EVENT(&event);
}

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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_IDLE_H
#define MT_SPM_IDLE_H
#include "mt_spm_internal.h"
typedef int (*spm_idle_conduct)(int state_id,
struct spm_lp_scen *spm_lp,
unsigned int *resource_req);
typedef int (*spm_idle_conduct_restore)(int state_id,
struct spm_lp_scen *spm_lp,
struct wake_status *status);
int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn);
void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
struct wake_status **status,
spm_idle_conduct_restore fn);
#endif

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/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
#include <drivers/uart.h>
#endif
#include <lib/mmio.h>
#ifndef MTK_PLAT_CIRQ_UNSUPPORT
#include <mtk_cirq.h>
#endif
#include <constraints/mt_spm_rc_internal.h>
#include <drivers/spm/mt_spm_resource_req.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_api.h>
#include <mt_spm.h>
#include <mt_spm_conservation.h>
#include <mt_spm_internal.h>
#include <mt_spm_reg.h>
#include <mt_spm_suspend.h>
#include <pcm_def.h>
#define SPM_SUSPEND_SLEEP_PCM_FLAG \
(SPM_FLAG_DISABLE_INFRA_PDN | \
SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_SLEEP_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
#define SPM_SUSPEND_PCM_FLAG \
(SPM_FLAG_DISABLE_VCORE_DVS | \
SPM_FLAG_DISABLE_VCORE_DFS | \
SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
SPM_FLAG_SRAM_SLEEP_CTRL)
#define SPM_SUSPEND_PCM_FLAG1 (SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH)
/* Suspend spm power control */
#define __WAKE_SRC_FOR_SUSPEND_COMMON__ ( \
(R12_PCM_TIMER) | \
(R12_KP_IRQ_B) | \
(R12_APWDT_EVENT_B) | \
(R12_MSDC_WAKEUP_B) | \
(R12_EINT_EVENT_B) | \
(R12_SBD_INTR_WAKEUP_B) | \
(R12_SSPM2SPM_WAKEUP_B) | \
(R12_SCP2SPM_WAKEUP_B) | \
(R12_ADSP2SPM_WAKEUP_B) | \
(R12_USBX_CDSC_B) | \
(R12_USBX_POWERDWN_B) | \
(R12_SYS_TIMER_EVENT_B) | \
(R12_EINT_EVENT_SECURE_B) | \
(R12_ECE_INT_HDMI_B) | \
(R12_SYS_CIRQ_IRQ_B) | \
(R12_PCIE_WAKEUPEVENT_B) | \
(R12_SPM_CPU_WAKEUPEVENT_B) | \
(R12_APUSYS_WAKE_HOST_B))
#if defined(CFG_MICROTRUST_TEE_SUPPORT)
#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
#else
#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__ | R12_SEJ_EVENT_B)
#endif
static struct pwr_ctrl suspend_ctrl = {
.wake_src = WAKE_SRC_FOR_SUSPEND,
/* SPM_AP_STANDBY_CON */
/* [0] */
.reg_wfi_op = 0,
/* [1] */
.reg_wfi_type = 0,
/* [2] */
.reg_mp0_cputop_idle_mask = 0,
/* [3] */
.reg_mp1_cputop_idle_mask = 0,
/* [4] */
.reg_mcusys_idle_mask = 0,
/* [25] */
.reg_md_apsrc_1_sel = 0,
/* [26] */
.reg_md_apsrc_0_sel = 0,
/* [29] */
.reg_conn_apsrc_sel = 0,
/* SPM_SRC_REQ */
/* [0] */
.reg_spm_apsrc_req = 0,
/* [1] */
.reg_spm_f26m_req = 0,
/* [3] */
.reg_spm_infra_req = 0,
/* [4] */
.reg_spm_vrf18_req = 0,
/* [7] */
.reg_spm_ddr_en_req = 0,
/* [8] */
.reg_spm_dvfs_req = 0,
/* [9] */
.reg_spm_sw_mailbox_req = 0,
/* [10] */
.reg_spm_sspm_mailbox_req = 0,
/* [11] */
.reg_spm_adsp_mailbox_req = 0,
/* [12] */
.reg_spm_scp_mailbox_req = 0,
/* SPM_SRC_MASK */
/* [0] */
.reg_sspm_srcclkena_0_mask_b = 1,
/* [1] */
.reg_sspm_infra_req_0_mask_b = 1,
/* [2] */
.reg_sspm_apsrc_req_0_mask_b = 0,
/* [3] */
.reg_sspm_vrf18_req_0_mask_b = 0,
/* [4] */
.reg_sspm_ddr_en_0_mask_b = 0,
/* [5] */
.reg_scp_srcclkena_mask_b = 1,
/* [6] */
.reg_scp_infra_req_mask_b = 1,
/* [7] */
.reg_scp_apsrc_req_mask_b = 1,
/* [8] */
.reg_scp_vrf18_req_mask_b = 1,
/* [9] */
.reg_scp_ddr_en_mask_b = 1,
/* [10] */
.reg_audio_dsp_srcclkena_mask_b = 1,
/* [11] */
.reg_audio_dsp_infra_req_mask_b = 1,
/* [12] */
.reg_audio_dsp_apsrc_req_mask_b = 1,
/* [13] */
.reg_audio_dsp_vrf18_req_mask_b = 1,
/* [14] */
.reg_audio_dsp_ddr_en_mask_b = 1,
/* [15] */
.reg_apu_srcclkena_mask_b = 1,
/* [16] */
.reg_apu_infra_req_mask_b = 1,
/* [17] */
.reg_apu_apsrc_req_mask_b = 0,
/* [18] */
.reg_apu_vrf18_req_mask_b = 1,
/* [19] */
.reg_apu_ddr_en_mask_b = 1,
/* [20] */
.reg_cpueb_srcclkena_mask_b = 1,
/* [21] */
.reg_cpueb_infra_req_mask_b = 1,
/* [22] */
.reg_cpueb_apsrc_req_mask_b = 1,
/* [23] */
.reg_cpueb_vrf18_req_mask_b = 1,
/* [24] */
.reg_cpueb_ddr_en_mask_b = 1,
/* [25] */
.reg_bak_psri_srcclkena_mask_b = 0,
/* [26] */
.reg_bak_psri_infra_req_mask_b = 0,
/* [27] */
.reg_bak_psri_apsrc_req_mask_b = 0,
/* [28] */
.reg_bak_psri_vrf18_req_mask_b = 0,
/* [29] */
.reg_bak_psri_ddr_en_mask_b = 0,
/* [30] */
.reg_cam_ddren_req_mask_b = 0,
/* [31] */
.reg_img_ddren_req_mask_b = 0,
/* SPM_SRC2_MASK */
/* [0] */
.reg_msdc0_srcclkena_mask_b = 1,
/* [1] */
.reg_msdc0_infra_req_mask_b = 1,
/* [2] */
.reg_msdc0_apsrc_req_mask_b = 1,
/* [3] */
.reg_msdc0_vrf18_req_mask_b = 1,
/* [4] */
.reg_msdc0_ddr_en_mask_b = 1,
/* [5] */
.reg_msdc1_srcclkena_mask_b = 1,
/* [6] */
.reg_msdc1_infra_req_mask_b = 1,
/* [7] */
.reg_msdc1_apsrc_req_mask_b = 1,
/* [8] */
.reg_msdc1_vrf18_req_mask_b = 1,
/* [9] */
.reg_msdc1_ddr_en_mask_b = 1,
/* [10] */
.reg_msdc2_srcclkena_mask_b = 1,
/* [11] */
.reg_msdc2_infra_req_mask_b = 1,
/* [12] */
.reg_msdc2_apsrc_req_mask_b = 1,
/* [13] */
.reg_msdc2_vrf18_req_mask_b = 1,
/* [14] */
.reg_msdc2_ddr_en_mask_b = 1,
/* [15] */
.reg_ufs_srcclkena_mask_b = 1,
/* [16] */
.reg_ufs_infra_req_mask_b = 1,
/* [17] */
.reg_ufs_apsrc_req_mask_b = 1,
/* [18] */
.reg_ufs_vrf18_req_mask_b = 1,
/* [19] */
.reg_ufs_ddr_en_mask_b = 1,
/* [20] */
.reg_usb_srcclkena_mask_b = 1,
/* [21] */
.reg_usb_infra_req_mask_b = 1,
/* [22] */
.reg_usb_apsrc_req_mask_b = 1,
/* [23] */
.reg_usb_vrf18_req_mask_b = 1,
/* [24] */
.reg_usb_ddr_en_mask_b = 1,
/* [25] */
.reg_pextp_p0_srcclkena_mask_b = 1,
/* [26] */
.reg_pextp_p0_infra_req_mask_b = 1,
/* [27] */
.reg_pextp_p0_apsrc_req_mask_b = 1,
/* [28] */
.reg_pextp_p0_vrf18_req_mask_b = 1,
/* [29] */
.reg_pextp_p0_ddr_en_mask_b = 1,
/* SPM_SRC3_MASK */
/* [0] */
.reg_pextp_p1_srcclkena_mask_b = 1,
/* [1] */
.reg_pextp_p1_infra_req_mask_b = 1,
/* [2] */
.reg_pextp_p1_apsrc_req_mask_b = 1,
/* [3] */
.reg_pextp_p1_vrf18_req_mask_b = 1,
/* [4] */
.reg_pextp_p1_ddr_en_mask_b = 1,
/* [5] */
.reg_gce0_infra_req_mask_b = 1,
/* [6] */
.reg_gce0_apsrc_req_mask_b = 1,
/* [7] */
.reg_gce0_vrf18_req_mask_b = 1,
/* [8] */
.reg_gce0_ddr_en_mask_b = 1,
/* [9] */
.reg_gce1_infra_req_mask_b = 1,
/* [10] */
.reg_gce1_apsrc_req_mask_b = 1,
/* [11] */
.reg_gce1_vrf18_req_mask_b = 1,
/* [12] */
.reg_gce1_ddr_en_mask_b = 1,
/* [13] */
.reg_spm_srcclkena_reserved_mask_b = 1,
/* [14] */
.reg_spm_infra_req_reserved_mask_b = 1,
/* [15] */
.reg_spm_apsrc_req_reserved_mask_b = 1,
/* [16] */
.reg_spm_vrf18_req_reserved_mask_b = 1,
/* [17] */
.reg_spm_ddr_en_reserved_mask_b = 1,
/* [18] */
.reg_disp0_apsrc_req_mask_b = 1,
/* [19] */
.reg_disp0_ddr_en_mask_b = 1,
/* [20] */
.reg_disp1_apsrc_req_mask_b = 1,
/* [21] */
.reg_disp1_ddr_en_mask_b = 1,
/* [22] */
.reg_disp2_apsrc_req_mask_b = 1,
/* [23] */
.reg_disp2_ddr_en_mask_b = 1,
/* [24] */
.reg_disp3_apsrc_req_mask_b = 1,
/* [25] */
.reg_disp3_ddr_en_mask_b = 1,
/* [26] */
.reg_infrasys_apsrc_req_mask_b = 0,
/* [27] */
.reg_infrasys_ddr_en_mask_b = 1,
/* [28] */
.reg_cg_check_srcclkena_mask_b = 1,
/* [29] */
.reg_cg_check_apsrc_req_mask_b = 1,
/* [30] */
.reg_cg_check_vrf18_req_mask_b = 1,
/* [31] */
.reg_cg_check_ddr_en_mask_b = 1,
/* SPM_SRC4_MASK */
/* [8:0] */
.reg_mcusys_merge_apsrc_req_mask_b = 0,
/* [17:9] */
.reg_mcusys_merge_ddr_en_mask_b = 0,
/* [19:18] */
.reg_dramc_md32_infra_req_mask_b = 3,
/* [21:20] */
.reg_dramc_md32_vrf18_req_mask_b = 3,
/* [23:22] */
.reg_dramc_md32_ddr_en_mask_b = 0,
/* [24] */
.reg_dvfsrc_event_trigger_mask_b = 1,
/* SPM_WAKEUP_EVENT_MASK2 */
/* [3:0] */
.reg_sc_sw2spm_wakeup_mask_b = 0,
/* [4] */
.reg_sc_adsp2spm_wakeup_mask_b = 0,
/* [8:5] */
.reg_sc_sspm2spm_wakeup_mask_b = 0,
/* [9] */
.reg_sc_scp2spm_wakeup_mask_b = 0,
/* [10] */
.reg_csyspwrup_ack_mask = 0,
/* [11] */
.reg_csyspwrup_req_mask = 1,
/* SPM_WAKEUP_EVENT_MASK */
/* [31:0] */
.reg_wakeup_event_mask = 0xC1382213,
/* SPM_WAKEUP_EVENT_EXT_MASK */
/* [31:0] */
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
/*sw flag setting */
.pcm_flags = SPM_SUSPEND_PCM_FLAG,
.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
};
struct spm_lp_scen __spm_suspend = {
.pwrctrl = &suspend_ctrl,
};
int mt_spm_suspend_mode_set(int mode, void *prv)
{
if (mode == MT_SPM_SUSPEND_SLEEP) {
suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
} else {
suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
}
return 0;
}
int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req)
{
int ret = 0;
/* if FMAudio, ADSP is active, change to sleep suspend mode */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP, NULL);
}
if ((ext_opand & MT_SPM_EX_OP_PERI_ON) != 0U) {
suspend_ctrl.pcm_flags |= SPM_FLAG_PERI_ON_IN_SUSPEND;
} else {
suspend_ctrl.pcm_flags &= ~SPM_FLAG_PERI_ON_IN_SUSPEND;
}
if ((ext_opand & MT_SPM_EX_OP_INFRA_ON) != 0U) {
suspend_ctrl.pcm_flags |= SPM_FLAG_DISABLE_INFRA_PDN;
} else {
suspend_ctrl.pcm_flags &= ~SPM_FLAG_DISABLE_INFRA_PDN;
}
#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
/* Notify UART to sleep */
mtk_uart_save();
#endif
ret = spm_conservation(state_id, ext_opand, &__spm_suspend, reosuce_req);
if (ret == 0) {
struct mt_lp_publish_event event = {
.id = MT_LPM_PUBEVENTS_SYS_POWER_OFF,
.val.u32 = 0U,
};
MT_LP_SUSPEND_PUBLISH_EVENT(&event);
}
return ret;
}
void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status)
{
struct mt_lp_publish_event event = {
.id = MT_LPM_PUBEVENTS_SYS_POWER_ON,
.val.u32 = 0U,
};
struct wake_status *st = NULL;
spm_conservation_finish(state_id, ext_opand, &__spm_suspend, &st);
#ifndef MTK_PLAT_SPM_UART_UNSUPPORT
/* Notify UART to wakeup */
mtk_uart_restore();
#endif
/* If FMAudio, ADSP is active, change back to suspend mode and counting in resume */
if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN, NULL);
}
if (status != NULL) {
*status = st;
}
MT_LP_SUSPEND_PUBLISH_EVENT(&event);
}

25
plat/mediatek/drivers/spm/mt8188/mt_spm_suspend.h Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright (c) 2023, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_SPM_SUSPEND_H
#define MT_SPM_SUSPEND_H
#include <mt_spm_internal.h>
struct suspend_dbg_ctrl {
uint32_t sleep_suspend_cnt;
};
enum mt_spm_suspend_mode {
MT_SPM_SUSPEND_SYSTEM_PDN = 0,
MT_SPM_SUSPEND_SLEEP,
};
int mt_spm_suspend_mode_set(int mode, void *prv);
int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, unsigned int reosuce_req);
void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, struct wake_status **status);
#endif

2
plat/mediatek/drivers/spm/mt8188/rules.mk
View File

@ -12,7 +12,7 @@ $(shell dirname ${LOCAL_DIR})
endef endef
UPPER_DIR := $(call GET_UPPER_DIR) UPPER_DIR := $(call GET_UPPER_DIR)
MT_SPM_FEATURE_SUPPORT := n MT_SPM_FEATURE_SUPPORT := y
MT_SPM_CIRQ_FEATURE_SUPPORT := n MT_SPM_CIRQ_FEATURE_SUPPORT := n
MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n MT_SPMFW_SPM_SRAM_SLEEP_SUPPORT := n
MT_SPM_SSPM_NOTIFIER_SUPPORT := y MT_SPM_SSPM_NOTIFIER_SUPPORT := y