mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-08-19 13:31:07 +02:00
Tegra: gic: fix MISRA defects
Main fixes:
* Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6]
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Force operands of an operator to the same type category [Rule 10.4]
* Fixed assert/if statements conditions to be essentially boolean [Rule 14.4]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Convert macros form headers to unsigned ints
Change-Id: I8051cc16499cece2039c9751bd347645f40f0901
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
5bd1a177dd
commit
9a8f05e47d
@ -24,7 +24,7 @@
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(GIC_HIGHEST_NS_PRIORITY << 24))
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static const irq_sec_cfg_t *g_irq_sec_ptr;
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static unsigned int g_num_irqs;
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static uint32_t g_num_irqs;
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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@ -32,7 +32,7 @@ static unsigned int g_num_irqs;
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******************************************************************************/
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void tegra_gic_cpuif_deactivate(void)
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{
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unsigned int val;
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uint32_t val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(TEGRA_GICC_BASE);
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@ -46,9 +46,9 @@ void tegra_gic_cpuif_deactivate(void)
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* Enable secure interrupts and set the priority mask register to allow all
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* interrupts to trickle in.
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******************************************************************************/
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static void tegra_gic_cpuif_setup(unsigned int gicc_base)
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static void tegra_gic_cpuif_setup(uint32_t gicc_base)
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{
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unsigned int val;
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uint32_t val;
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val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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@ -61,14 +61,14 @@ static void tegra_gic_cpuif_setup(unsigned int gicc_base)
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base)
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static void tegra_gic_pcpu_distif_setup(uint32_t gicd_base)
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{
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unsigned int index, sec_ppi_sgi_mask = 0;
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uint32_t index, sec_ppi_sgi_mask = 0;
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assert(gicd_base);
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assert(gicd_base != 0U);
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/* Setup PPI priorities doing four at a time */
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for (index = 0; index < 32; index += 4) {
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for (index = 0U; index < 32U; index += 4U) {
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gicd_write_ipriorityr(gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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@ -87,9 +87,9 @@ static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base)
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* cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
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* It then enables the secure GIC distributor interface.
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******************************************************************************/
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static void tegra_gic_distif_setup(unsigned int gicd_base)
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static void tegra_gic_distif_setup(uint32_t gicd_base)
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{
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unsigned int index, num_ints, irq_num;
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uint32_t index, num_ints, irq_num;
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uint8_t target_cpus;
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uint32_t val;
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@ -99,22 +99,23 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
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* number of IT_LINES
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*/
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num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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num_ints = (num_ints + 1) << 5;
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for (index = MIN_SPI_ID; index < num_ints; index += 32)
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gicd_write_igroupr(gicd_base, index, ~0);
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num_ints = (num_ints + 1U) << 5;
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for (index = MIN_SPI_ID; index < num_ints; index += 32U) {
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gicd_write_igroupr(gicd_base, index, 0xFFFFFFFFU);
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}
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/* Setup SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4) {
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for (index = MIN_SPI_ID; index < num_ints; index += 4U) {
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gicd_write_ipriorityr(gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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/* Configure SPI secure interrupts now */
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if (g_irq_sec_ptr) {
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if (g_irq_sec_ptr != NULL) {
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = (g_irq_sec_ptr + index)->irq;
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target_cpus = (g_irq_sec_ptr + index)->target_cpus;
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for (index = 0U; index < g_num_irqs; index++) {
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irq_num = g_irq_sec_ptr[index].irq;
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target_cpus = (uint8_t)g_irq_sec_ptr[index].target_cpus;
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if (irq_num >= MIN_SPI_ID) {
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@ -122,14 +123,15 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
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gicd_clr_igroupr(gicd_base, irq_num);
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/* Configure SPI priority */
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mmio_write_8(gicd_base + GICD_IPRIORITYR +
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irq_num,
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mmio_write_8((uint64_t)gicd_base +
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(uint64_t)GICD_IPRIORITYR +
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(uint64_t)irq_num,
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GIC_HIGHEST_SEC_PRIORITY &
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GIC_PRI_MASK);
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/* Configure as level triggered */
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val = gicd_read_icfgr(gicd_base, irq_num);
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val |= (3 << ((irq_num & 0xF) << 1));
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val |= (3U << ((irq_num & 0xFU) << 1U));
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gicd_write_icfgr(gicd_base, irq_num, val);
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/* Route SPI to the target CPUs */
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@ -153,7 +155,7 @@ static void tegra_gic_distif_setup(unsigned int gicd_base)
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gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
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}
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void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs)
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void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs)
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{
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g_irq_sec_ptr = irq_sec_ptr;
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g_num_irqs = num_irqs;
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@ -172,12 +174,12 @@ void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs)
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* SCR_EL3 to control its routing to EL3. The interrupt line is represented as
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* the bit position of the IRQ or FIQ bit in the SCR_EL3.
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******************************************************************************/
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uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
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static uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
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uint32_t security_state)
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{
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assert(type == INTR_TYPE_S_EL1 ||
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type == INTR_TYPE_EL3 ||
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type == INTR_TYPE_NS);
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assert((type == INTR_TYPE_S_EL1) ||
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(type == INTR_TYPE_EL3) ||
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(type == INTR_TYPE_NS));
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assert(sec_state_is_valid(security_state));
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@ -199,25 +201,29 @@ uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
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* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t tegra_gic_get_pending_interrupt_type(void)
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static uint32_t tegra_gic_get_pending_interrupt_type(void)
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{
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uint32_t id;
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unsigned int index;
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uint32_t index;
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uint32_t ret = INTR_TYPE_NS;
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id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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/* get the interrupt type */
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if (id < 1022) {
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for (index = 0; index < g_num_irqs; index++) {
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if (id == (g_irq_sec_ptr + index)->irq)
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return (g_irq_sec_ptr + index)->type;
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if (id < 1022U) {
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for (index = 0U; index < g_num_irqs; index++) {
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if (id == g_irq_sec_ptr[index].irq) {
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ret = g_irq_sec_ptr[index].type;
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break;
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}
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}
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} else {
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if (id == GIC_SPURIOUS_INTERRUPT) {
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ret = INTR_TYPE_INVAL;
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}
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}
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if (id == GIC_SPURIOUS_INTERRUPT)
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return INTR_TYPE_INVAL;
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return INTR_TYPE_NS;
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return ret;
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}
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/*******************************************************************************
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@ -225,30 +231,32 @@ uint32_t tegra_gic_get_pending_interrupt_type(void)
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* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t tegra_gic_get_pending_interrupt_id(void)
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static uint32_t tegra_gic_get_pending_interrupt_id(void)
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{
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uint32_t id;
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uint32_t id, ret;
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id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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if (id < 1022)
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return id;
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if (id < 1022UL) {
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ret = id;
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} else if (id == 1023UL) {
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ret = 0xFFFFFFFFUL; /* INTR_ID_UNAVAILABLE */
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} else {
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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ret = gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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}
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if (id == 1023)
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return INTR_ID_UNAVAILABLE;
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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return gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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return ret;
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}
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/*******************************************************************************
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* This functions reads the GIC cpu interface Interrupt Acknowledge register
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* to start handling the pending interrupt. It returns the contents of the IAR.
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******************************************************************************/
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uint32_t tegra_gic_acknowledge_interrupt(void)
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static uint32_t tegra_gic_acknowledge_interrupt(void)
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{
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return gicc_read_IAR(TEGRA_GICC_BASE);
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}
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@ -257,7 +265,7 @@ uint32_t tegra_gic_acknowledge_interrupt(void)
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* This functions writes the GIC cpu interface End Of Interrupt register with
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* the passed value to finish handling the active interrupt
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******************************************************************************/
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void tegra_gic_end_of_interrupt(uint32_t id)
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static void tegra_gic_end_of_interrupt(uint32_t id)
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{
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gicc_write_EOIR(TEGRA_GICC_BASE, id);
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}
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@ -267,22 +275,25 @@ void tegra_gic_end_of_interrupt(uint32_t id)
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 or group1.
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******************************************************************************/
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uint32_t tegra_gic_get_interrupt_type(uint32_t id)
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static uint32_t tegra_gic_get_interrupt_type(uint32_t id)
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{
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uint32_t group;
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unsigned int index;
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uint32_t index;
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uint32_t ret = INTR_TYPE_NS;
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group = gicd_get_igroupr(TEGRA_GICD_BASE, id);
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/* get the interrupt type */
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if (group == GRP0) {
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for (index = 0; index < g_num_irqs; index++) {
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if (id == (g_irq_sec_ptr + index)->irq)
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return (g_irq_sec_ptr + index)->type;
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for (index = 0U; index < g_num_irqs; index++) {
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if (id == g_irq_sec_ptr[index].irq) {
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ret = g_irq_sec_ptr[index].type;
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break;
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}
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}
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}
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return INTR_TYPE_NS;
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return ret;
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}
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#else
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@ -71,8 +71,8 @@ int tegra_fiq_get_intr_context(void);
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void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
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/* Declarations for tegra_gic.c */
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void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs);
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void tegra_gic_cpuif_deactivate(void);
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void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs);
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/* Declarations for tegra_security.c */
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void tegra_security_setup(void);
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