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fix(versal): sync location based on IPI_ID macros

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IPI_ID_* macros available at include/plat_ipi.h are using PMC/APU/RPU0..
order which is not how versal_ipi_table array is composed. That's why
swap APU and PMC to follow the same order as is described by macros.

Change-Id: Ieaa3a967650e298e7cff45fafde0df96294c09fe
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Michal Simek 2023-02-08 13:34:47 +01:00 committed by Joanna Farley
parent 15f49cb49d
commit 92a43bdf36
1 changed files with 6 additions and 6 deletions
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12
plat/xilinx/versal/versal_ipi.c
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@ -20,16 +20,16 @@
/* versal ipi configuration table */ /* versal ipi configuration table */
static const struct ipi_config versal_ipi_table[] = { static const struct ipi_config versal_ipi_table[] = {
/* A72 IPI */ /* PMC IPI */
[IPI_ID_APU] = { [IPI_ID_PMC] = {
.ipi_bit_mask = IPI0_TRIG_BIT, .ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE, .ipi_reg_base = IPI0_REG_BASE,
.secure_only = 0U, .secure_only = 0U,
}, },
/* PMC IPI */ /* A72 IPI */
[IPI_ID_PMC] = { [IPI_ID_APU] = {
.ipi_bit_mask = PMC_IPI_TRIG_BIT, .ipi_bit_mask = IPI0_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE, .ipi_reg_base = IPI0_REG_BASE,
.secure_only = 0U, .secure_only = 0U,
}, },