From 77b6801966d203e09ca118fad42543e934d73e6f Mon Sep 17 00:00:00 2001 From: Flora Fu Date: Tue, 20 Apr 2021 11:45:56 +0800 Subject: [PATCH 1/4] feat(plat/mediatek/apu): setup mt8192 APU_S_S_4 and APU_S_S_5 permission Setup APU_S_S_4/APU_S_S_5 permission as SEC_RW_ONLY. Signed-off-by: Flora Fu Change-Id: I6c50b2913bf34270a1b0ffaf0e0c435fee192a4c --- plat/mediatek/mt8192/drivers/devapc/devapc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c index c7dbbee17..8312bb84a 100644 --- a/plat/mediatek/mt8192/drivers/devapc/devapc.c +++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c @@ -82,12 +82,12 @@ DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3", FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), From 2671f3187249d641c55929c812d6691aeeff502a Mon Sep 17 00:00:00 2001 From: Flora Fu Date: Tue, 20 Apr 2021 11:23:21 +0800 Subject: [PATCH 2/4] feat(plat/mediatek/apu): add mt8192 APU iommap regions Add APU iommap settings for reviser, apu_ao and devapc control wrapper. Signed-off-by: Flora Fu Change-Id: Ie8e6a197c0f440f9e4ee8101202283a2dbf501a6 --- plat/mediatek/mt8192/aarch64/platform_common.c | 8 ++++++++ plat/mediatek/mt8192/include/platform_def.h | 10 ++++++++++ 2 files changed, 18 insertions(+) diff --git a/plat/mediatek/mt8192/aarch64/platform_common.c b/plat/mediatek/mt8192/aarch64/platform_common.c index ffa10fe11..fc98871ec 100644 --- a/plat/mediatek/mt8192/aarch64/platform_common.c +++ b/plat/mediatek/mt8192/aarch64/platform_common.c @@ -21,6 +21,14 @@ const mmap_region_t plat_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), { 0 } }; diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h index 320124f07..ec377b5ac 100644 --- a/plat/mediatek/mt8192/include/platform_def.h +++ b/plat/mediatek/mt8192/include/platform_def.h @@ -26,6 +26,16 @@ #define MTK_MCDI_SRAM_BASE 0x11B000 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 +#define APUSYS_BASE 0x19000000 +#define APUSYS_SCTRL_REVISER_BASE 0x19021000 +#define APUSYS_SCTRL_REVISER_SIZE 0x1000 +#define APUSYS_APU_S_S_4_BASE 0x190F2000 +#define APUSYS_APU_S_S_4_SIZE 0x1000 +#define APUSYS_APC_AO_WRAPPER_BASE 0x190F8000 +#define APUSYS_APC_AO_WRAPPER_SIZE 0x1000 +#define APUSYS_NOC_DAPC_AO_BASE 0x190FC000 +#define APUSYS_NOC_DAPC_AO_SIZE 0x1000 + #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) #define GPIO_BASE (IO_PHYS + 0x00005000) From ca4c0c2e78eb19d442de4608d9096a755b540a37 Mon Sep 17 00:00:00 2001 From: Flora Fu Date: Tue, 20 Apr 2021 12:53:15 +0800 Subject: [PATCH 3/4] feat(plat/mediatek/apu): add mt8192 APU SiP call support Add APU SiP call support for start/stop mcu. Signed-off-by: Flora Fu Change-Id: Ibf93d8ccf22c414de3093cee9e13f7668588f69e Signed-off-by: Pi-Cheng Chen --- plat/mediatek/common/mtk_sip_svc.h | 4 ++ .../mt8192/drivers/apusys/mtk_apusys.c | 68 +++++++++++++++++++ .../mt8192/drivers/apusys/mtk_apusys.h | 42 ++++++++++++ plat/mediatek/mt8192/plat_sip_calls.c | 7 ++ plat/mediatek/mt8192/platform.mk | 2 + 5 files changed, 123 insertions(+) create mode 100644 plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c create mode 100644 plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h diff --git a/plat/mediatek/common/mtk_sip_svc.h b/plat/mediatek/common/mtk_sip_svc.h index 45ce281eb..74b17b645 100644 --- a/plat/mediatek/common/mtk_sip_svc.h +++ b/plat/mediatek/common/mtk_sip_svc.h @@ -35,6 +35,10 @@ #define MTK_SIP_VCORE_CONTROL_ARCH32 0x82000506 #define MTK_SIP_VCORE_CONTROL_ARCH64 0xC2000506 +/* APUSYS SMC call */ +#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E +#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E + /* Mediatek SiP Calls error code */ enum { MTK_SIP_E_SUCCESS = 0, diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c new file mode 100644 index 000000000..782aa5f9b --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + uint32_t *ret1) +{ + uint32_t request_ops; + + request_ops = (uint32_t)x1; + INFO("[APUSYS] ops=0x%x\n", request_ops); + + switch (request_ops) { + case MTK_SIP_APU_START_MCU: + /* setup addr[33:32] in reviser */ + mmio_write_32(REVISER_SECUREFW_CTXT, 0U); + mmio_write_32(REVISER_USDRFW_CTXT, 0U); + + /* setup secure sideband */ + mmio_write_32(AO_SEC_FW, + (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) | + (0U << SEC_FW_DOMAIN_SHIFT)); + + /* setup boot address */ + mmio_write_32(AO_MD32_BOOT_CTRL, 0U); + + /* setup pre-define region */ + mmio_write_32(AO_MD32_PRE_DEFINE, + (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) | + (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) | + (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) | + (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G)); + + /* release runstall */ + mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN); + + INFO("[APUSYS] reviser_ctxt=%x,%x\n", + mmio_read_32(REVISER_SECUREFW_CTXT), + mmio_read_32(REVISER_USDRFW_CTXT)); + INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n", + mmio_read_32(AO_SEC_FW), + mmio_read_32(AO_MD32_BOOT_CTRL), + mmio_read_32(AO_MD32_PRE_DEFINE), + mmio_read_32(AO_MD32_SYS_CTRL)); + break; + case MTK_SIP_APU_STOP_MCU: + /* hold runstall */ + mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL); + + INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n", + mmio_read_32(AO_MD32_BOOT_CTRL), + mmio_read_32(AO_MD32_SYS_CTRL)); + break; + default: + ERROR("%s, unknown request_ops = %x\n", __func__, request_ops); + break; + } + + return 0UL; +} diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h new file mode 100644 index 000000000..95fac4ace --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_APUSYS_H__ +#define __MTK_APUSYS_H__ + +#include + +/* setup the SMC command ops */ +#define MTK_SIP_APU_START_MCU 0x00U +#define MTK_SIP_APU_STOP_MCU 0x01U + +/* AO Register */ +#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) +#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) +#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) +#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) + +#define PRE_DEFINE_CACHE_TCM 0x3U +#define PRE_DEFINE_CACHE 0x2U +#define PRE_DEFINE_SHIFT_0G 0U +#define PRE_DEFINE_SHIFT_1G 2U +#define PRE_DEFINE_SHIFT_2G 4U +#define PRE_DEFINE_SHIFT_3G 6U + +#define SEC_FW_NON_SECURE 1U +#define SEC_FW_SHIFT_NS 4U +#define SEC_FW_DOMAIN_SHIFT 0U + +#define SYS_CTRL_RUN 0U +#define SYS_CTRL_STALL 1U + +/* Reviser Register */ +#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300) +#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304) + +uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + uint32_t *ret1); +#endif /* __MTK_APUSYS_H__ */ diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c index 360ad0f00..f567f02ef 100644 --- a/plat/mediatek/mt8192/plat_sip_calls.c +++ b/plat/mediatek/mt8192/plat_sip_calls.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include "plat_sip_calls.h" @@ -20,6 +21,7 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, u_register_t flags) { uint64_t ret; + uint32_t rnd_val0 = 0U; switch (smc_fid) { case MTK_SIP_VCORE_CONTROL_ARCH32: @@ -27,6 +29,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); SMC_RET2(handle, ret, x4); break; + case MTK_SIP_APUSYS_CONTROL_AARCH32: + case MTK_SIP_APUSYS_CONTROL_AARCH64: + ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); + SMC_RET2(handle, ret, rnd_val0); + break; default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); break; diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk index 1a57ea850..0add415d8 100644 --- a/plat/mediatek/mt8192/platform.mk +++ b/plat/mediatek/mt8192/platform.mk @@ -16,6 +16,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT}/common/lpm/ \ -I${MTK_PLAT_SOC}/include/ \ -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/apusys/ \ -I${MTK_PLAT_SOC}/drivers/dcm \ -I${MTK_PLAT_SOC}/drivers/devapc \ -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ @@ -62,6 +63,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_sip_calls.c \ + ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \ From f46e1f18539d6d992c82ae605c2cd2a1d0757fa4 Mon Sep 17 00:00:00 2001 From: Flora Fu Date: Tue, 20 Apr 2021 18:08:35 +0800 Subject: [PATCH 4/4] feat(plat/mediatek/apu): add mt8192 APU device apc driver Add APU device apc driver and setup permission. Signed-off-by: Flora Fu Change-Id: I2bbdb69d11267e4252b2138b5c5ac8faf752740f --- .../mt8192/drivers/apusys/mtk_apusys_apc.c | 571 ++++++++++++++++++ .../mt8192/drivers/apusys/mtk_apusys_apc.h | 12 + .../drivers/apusys/mtk_apusys_apc_def.h | 110 ++++ plat/mediatek/mt8192/drivers/devapc/devapc.c | 4 + plat/mediatek/mt8192/platform.mk | 1 + 5 files changed, 698 insertions(+) create mode 100644 plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c create mode 100644 plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h create mode 100644 plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c new file mode 100644 index 000000000..245d5126b --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c @@ -0,0 +1,571 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = { +/* 0~3 */ +APUSYS_APC_AO_ATTR("slv07-0", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv07-1", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv07-2", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv07-3", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), + +/* 16~18 */ +APUSYS_APC_AO_ATTR("slv01-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv01-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv01-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 19~21 */ +APUSYS_APC_AO_ATTR("slv00-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv00-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv00-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 22~26 */ +APUSYS_APC_AO_ATTR("slv02-0", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-1", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-2", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-3", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-4", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +}; + +static int32_t set_slave_noc_dapc(uint32_t slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + uintptr_t base; + uint32_t clr_bit; + uint32_t set_bit; + int32_t ret; + + if (perm >= PERM_NUM) { + ERROR("[NOC_DAPC] perm type:0x%x is not supported!\n", perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = perm << (apc_set_index * 2); + + if ((slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM) && + (domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM)) { + base = APUSYS_NOC_DAPC_AO_BASE + + (domain_id * 0x40) + (apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + ERROR("[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_noc_dapc(void) +{ + uint32_t reg_num; + uint32_t d, i; + + reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM / + APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) { + INFO("[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_NOC_DAPC_AO_BASE + + (d * 0x40) + (i * 4))); + } + } + + INFO("[NOCDAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_NOC_DAPC_CON)); +} + +static const struct APC_DOM_16 APUSYS_AO_Devices[] = { + +/* 0 */ +APUSYS_APC_AO_ATTR("apusys_ao-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-2", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-4", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-5", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_apb_s-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_apb_s-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_apb_s-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_debug_apb", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +APUSYS_APC_AO_ATTR("apu_conn_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_sctrl_reviser", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_sema_stimer", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_emi_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_adl", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma_lite0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma_lite1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_dapc_ao", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +APUSYS_APC_AO_ATTR("apu_dapc", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("infra_bcrm", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apb_dbg_ctl", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("noc_dapc", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_noc_bcrm", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_noc_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core0_config-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core0_config-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core1_config-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core1_config-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +APUSYS_APC_AO_ATTR("mdla0_apb-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("mdla0_apb-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("mdla0_apb-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("mdla0_apb-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r1", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r2", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r3", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r4", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_rsi2_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +APUSYS_APC_AO_ATTR("apu_ssc2_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vp6_core0_debug_apb", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vp6_core1_debug_apb", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +}; + +static int32_t set_slave_apc(uint32_t slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + uintptr_t base; + uint32_t clr_bit; + uint32_t set_bit; + int32_t ret; + + if (perm >= PERM_NUM) { + ERROR("[APUAPC] perm type:0x%x is not supported!\n", perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = perm << (apc_set_index * 2); + + if ((slave < APUSYS_APC_SYS0_AO_SLAVE_NUM) && + (domain_id < APUSYS_APC_SYS0_AO_DOM_NUM)) { + base = APUSYS_APC_AO_BASE + + (domain_id * 0x40) + (apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + ERROR("[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_ao_apc(void) +{ + uint32_t reg_num; + uint32_t d, i; + + reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM / + APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) { + INFO("[APUAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_APC_AO_BASE + + (d * 0x40) + (i * 4))); + } + } + INFO("[APUAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_APC_CON)); +} + +static int32_t set_apusys_noc_dapc(void) +{ + int32_t ret = 0; + uint32_t i; + uint32_t index; + + for (i = 0U; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) { + if (i < APUSYS_NOC_DAPC_GAP_BOUNDARY) { + index = i; + } else { + index = i + APUSYS_NOC_DAPC_JUMP_GAP; + } + ret += set_slave_noc_dapc(index, DOMAIN_0, + APUSYS_NOC_DAPC_AO[i].d0_permission); + ret += set_slave_noc_dapc(index, DOMAIN_1, + APUSYS_NOC_DAPC_AO[i].d1_permission); + ret += set_slave_noc_dapc(index, DOMAIN_2, + APUSYS_NOC_DAPC_AO[i].d2_permission); + ret += set_slave_noc_dapc(index, DOMAIN_3, + APUSYS_NOC_DAPC_AO[i].d3_permission); + ret += set_slave_noc_dapc(index, DOMAIN_4, + APUSYS_NOC_DAPC_AO[i].d4_permission); + ret += set_slave_noc_dapc(index, DOMAIN_5, + APUSYS_NOC_DAPC_AO[i].d5_permission); + ret += set_slave_noc_dapc(index, DOMAIN_6, + APUSYS_NOC_DAPC_AO[i].d6_permission); + ret += set_slave_noc_dapc(index, DOMAIN_7, + APUSYS_NOC_DAPC_AO[i].d7_permission); + ret += set_slave_noc_dapc(index, DOMAIN_8, + APUSYS_NOC_DAPC_AO[i].d8_permission); + ret += set_slave_noc_dapc(index, DOMAIN_9, + APUSYS_NOC_DAPC_AO[i].d9_permission); + ret += set_slave_noc_dapc(index, DOMAIN_10, + APUSYS_NOC_DAPC_AO[i].d10_permission); + ret += set_slave_noc_dapc(index, DOMAIN_11, + APUSYS_NOC_DAPC_AO[i].d11_permission); + ret += set_slave_noc_dapc(index, DOMAIN_12, + APUSYS_NOC_DAPC_AO[i].d12_permission); + ret += set_slave_noc_dapc(index, DOMAIN_13, + APUSYS_NOC_DAPC_AO[i].d13_permission); + ret += set_slave_noc_dapc(index, DOMAIN_14, + APUSYS_NOC_DAPC_AO[i].d14_permission); + ret += set_slave_noc_dapc(index, DOMAIN_15, + APUSYS_NOC_DAPC_AO[i].d15_permission); + } + + return ret; +} + +static int32_t set_apusys_ao_apc(void) +{ + int32_t ret = 0; + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) { + ret += set_slave_apc(i, DOMAIN_0, + APUSYS_AO_Devices[i].d0_permission); + ret += set_slave_apc(i, DOMAIN_1, + APUSYS_AO_Devices[i].d1_permission); + ret += set_slave_apc(i, DOMAIN_2, + APUSYS_AO_Devices[i].d2_permission); + ret += set_slave_apc(i, DOMAIN_3, + APUSYS_AO_Devices[i].d3_permission); + ret += set_slave_apc(i, DOMAIN_4, + APUSYS_AO_Devices[i].d4_permission); + ret += set_slave_apc(i, DOMAIN_5, + APUSYS_AO_Devices[i].d5_permission); + ret += set_slave_apc(i, DOMAIN_6, + APUSYS_AO_Devices[i].d6_permission); + ret += set_slave_apc(i, DOMAIN_7, + APUSYS_AO_Devices[i].d7_permission); + ret += set_slave_apc(i, DOMAIN_8, + APUSYS_AO_Devices[i].d8_permission); + ret += set_slave_apc(i, DOMAIN_9, + APUSYS_AO_Devices[i].d9_permission); + ret += set_slave_apc(i, DOMAIN_10, + APUSYS_AO_Devices[i].d10_permission); + ret += set_slave_apc(i, DOMAIN_11, + APUSYS_AO_Devices[i].d11_permission); + ret += set_slave_apc(i, DOMAIN_12, + APUSYS_AO_Devices[i].d12_permission); + ret += set_slave_apc(i, DOMAIN_13, + APUSYS_AO_Devices[i].d13_permission); + ret += set_slave_apc(i, DOMAIN_14, + APUSYS_AO_Devices[i].d14_permission); + ret += set_slave_apc(i, DOMAIN_15, + APUSYS_AO_Devices[i].d15_permission); + } + + return ret; +} + +static void set_apusys_apc_lock(void) +{ + uint32_t set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER; + + /* Lock apu_sctrl_reviser */ + set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5); + apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0); +} + +void set_apusys_apc(void) +{ + int32_t ret = 0; + + /* Check violation status */ + INFO("[APUAPC] vio %d\n", apuapc_readl(APUSYS_APC_CON) & 0x80000000); + + /* Initial Permission */ + ret = set_apusys_ao_apc(); + INFO("[APUAPC] %s - %s!\n", "set_apusys_ao_apc", + ret ? "FAILED" : "SUCCESS"); + + /* Lock */ + set_apusys_apc_lock(); + + /* Initial NoC Permission */ + ret = set_apusys_noc_dapc(); + INFO("[APUAPC] %s - %s!\n", "set_apusys_noc_dapc", + ret ? "FAILED" : "SUCCESS"); + + /* Dump Permission */ + dump_apusys_ao_apc(); + dump_apusys_noc_dapc(); + + INFO("[APUAPC] %s done\n", __func__); +} diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h new file mode 100644 index 000000000..ff7a9fa40 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_APUSYS_APC_H__ +#define __MTK_APUSYS_APC_H__ + +void set_apusys_apc(void); + +#endif /* __MTK_APUSYS_APC_H__ */ diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h new file mode 100644 index 000000000..b392d6a5c --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_APUSYS_APC_DEF_H__ +#define __MTK_APUSYS_APC_DEF_H__ + +#include + +enum APUSYS_APC_ERR_STATUS { + APUSYS_APC_OK = 0x0, + + APUSYS_APC_ERR_GENERIC = 0x1000, + APUSYS_APC_ERR_INVALID_CMD = 0x1001, + APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002, + APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003, + APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004, + APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005, + APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006, + APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007, +}; + +enum APUSYS_APC_PERM_TYPE { + NO_PROTECTION = 0U, + SEC_RW_ONLY = 1U, + SEC_RW_NS_R = 2U, + FORBIDDEN = 3U, + PERM_NUM = 4U, +}; + +enum APUSYS_APC_DOMAIN_ID { + DOMAIN_0 = 0U, + DOMAIN_1 = 1U, + DOMAIN_2 = 2U, + DOMAIN_3 = 3U, + DOMAIN_4 = 4U, + DOMAIN_5 = 5U, + DOMAIN_6 = 6U, + DOMAIN_7 = 7U, + DOMAIN_8 = 8U, + DOMAIN_9 = 9U, + DOMAIN_10 = 10U, + DOMAIN_11 = 11U, + DOMAIN_12 = 12U, + DOMAIN_13 = 13U, + DOMAIN_14 = 14U, + DOMAIN_15 = 15U, +}; + +struct APC_DOM_16 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; + unsigned char d4_permission; + unsigned char d5_permission; + unsigned char d6_permission; + unsigned char d7_permission; + unsigned char d8_permission; + unsigned char d9_permission; + unsigned char d10_permission; + unsigned char d11_permission; + unsigned char d12_permission; + unsigned char d13_permission; + unsigned char d14_permission; + unsigned char d15_permission; +}; + +#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \ + (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \ + (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \ + (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \ + (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \ + (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \ + (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15} + +#define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) +#define apuapc_readl(REG) mmio_read_32((uintptr_t)REG) + +/* APUSYS APC AO Registers */ +#define APUSYS_APC_AO_BASE APUSYS_APC_AO_WRAPPER_BASE +#define APUSYS_APC_CON (APUSYS_APC_AO_BASE + 0x00F00) +#define APUSYS_SYS0_APC_LOCK_0 (APUSYS_APC_AO_BASE + 0x00700) + +/* APUSYS NOC_DPAC_AO Registers */ +#define APUSYS_NOC_DAPC_CON (APUSYS_NOC_DAPC_AO_BASE + 0x00F00) + +#define APUSYS_NOC_DAPC_GAP_BOUNDARY 4U +#define APUSYS_NOC_DAPC_JUMP_GAP 12U + +#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_APC_SYS0_AO_DOM_NUM 16U +#define APUSYS_APC_SYS0_AO_SLAVE_NUM 59U + +#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 11U +#define APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5 5U + +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U + +#endif /* __MTK_APUSYS_APC_DEF_H__ */ diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c index 8312bb84a..b11f272ab 100644 --- a/plat/mediatek/mt8192/drivers/devapc/devapc.c +++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c @@ -9,6 +9,7 @@ #include #include +#include /* Infra_ao */ static const struct APC_INFRA_PERI_DOM_16 INFRA_AO_SYS0_Devices[] = { @@ -2839,5 +2840,8 @@ void devapc_init(void) dump_peri_ao2_apc(); dump_peri_par_ao_apc(); + /* Setup APUSYS Permission */ + set_apusys_apc(); + INFO("[DEVAPC] %s done\n", __func__); } diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk index 0add415d8..7761a55bf 100644 --- a/plat/mediatek/mt8192/platform.mk +++ b/plat/mediatek/mt8192/platform.mk @@ -64,6 +64,7 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_sip_calls.c \ ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \ + ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys_apc.c \ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \