fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
  and now two.

- This patch updates the value of open power switches from
  0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
This commit is contained in:
Christine Gharzuzi 2018-07-25 16:06:10 +03:00 committed by Konstantin Porotchkin
parent c35442690c
commit 5cf6fafe22

View File

@ -79,7 +79,7 @@ enum CPU_ID {
#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1
#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 0 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 0
#else #else
#define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 0 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 0
#define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31 #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31
#endif #endif
@ -106,7 +106,7 @@ enum CPU_ID {
#define AP807_PWRC_LDO_CR0_OFFSET 16 #define AP807_PWRC_LDO_CR0_OFFSET 16
#define AP807_PWRC_LDO_CR0_MASK \ #define AP807_PWRC_LDO_CR0_MASK \
(0xff << AP807_PWRC_LDO_CR0_OFFSET) (0xff << AP807_PWRC_LDO_CR0_OFFSET)
#define AP807_PWRC_LDO_CR0_VAL 0xfd #define AP807_PWRC_LDO_CR0_VAL 0xfc
/* /*
* Power down CPU: * Power down CPU: