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plat: marvell: ap807: use correct address for MCIx4 register

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The AP807 uses different register offset for MCIx4 register, reflect it
in the code.

Change-Id: Ic7e44fede3c69083e8629741e7c440b1ae08c35f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
This commit is contained in:
Grzegorz Jaszczyk 2019-01-13 15:29:10 +02:00 committed by Marcin Wojtas
parent dc402531ef
commit 2da75ae117
1 changed files with 6 additions and 1 deletions
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7
drivers/marvell/mochi/ap807_setup.c
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@ -31,6 +31,11 @@
#define DSS_CR0 (MVEBU_RFU_BASE + 0x100) #define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
#define DVM_48BIT_VA_ENABLE (1 << 21) #define DVM_48BIT_VA_ENABLE (1 << 21)
/* SoC RFU / IHBx4 Control */
#define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \
0x4258 + (unit_id * 0x4))
/* Secure MoChi incoming access */ /* Secure MoChi incoming access */
#define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
#define SEC_MOCHI_IN_ACC_IHB0_EN (1) #define SEC_MOCHI_IN_ACC_IHB0_EN (1)
@ -124,7 +129,7 @@ static void mci_remap_indirect_access_base(void)
uint32_t mci; uint32_t mci;
for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++)
mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), mmio_write_32(MCIX4_807_REG_START_ADDR_REG(mci),
MVEBU_MCI_REG_BASE_REMAP(mci) >> MVEBU_MCI_REG_BASE_REMAP(mci) >>
MCI_REMAP_OFF_SHIFT); MCI_REMAP_OFF_SHIFT);
} }