From 2bcde264f36dfff55827171cb54bf6684643bdfc Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 17 Dec 2019 16:09:00 +0200 Subject: [PATCH] drivers/marvell/mochi: add support for cn913x in PCIe EP mode Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc Signed-off-by: Konstantin Porotchkin Reviewed-on: https://sj1git1.cavium.com/20453 Tested-by: sa_ip-sw-jenkins Reviewed-by: Stefan Chulski --- drivers/marvell/mochi/cp110_setup.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index 54bc6674f..906df6680 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -186,8 +186,9 @@ static void cp110_pcie_clk_cfg(uintptr_t base) pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET; pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET; - /* CP110 revision A2 */ - if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) { + /* CP110 revision A2 or CN913x */ + if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 || + cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) { /* * PCIe Reference Clock Buffer Control register must be * set according to the clock direction (input/output)