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fix(mt8186): move SSPM base register definition to platform_def.h

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- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ibb0291ce7b7426068392e90bd70f29d1a90d5297
This commit is contained in:
Yidi Lin 2022-07-08 16:16:09 +08:00
parent 37d87416aa
commit 2a2b51d8f7
3 changed files with 5 additions and 7 deletions
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2
plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c
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@ -11,7 +11,7 @@
#include <mt_spm_sspm_intc.h>
#include <sspm_reg.h>
#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_3_BASE + x)
#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)

6
plat/mediatek/mt8186/include/platform_def.h
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@ -1,6 +1,6 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -26,6 +26,8 @@
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
#define SSPM_MCDI_SHARE_SRAM (IO_PHYS + 0x00420000)
#define SSPM_CFGREG_BASE (IO_PHYS + 0x00440000) /* SSPM view: 0x30040000 */
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define VPPSYS0_BASE (IO_PHYS + 0x04000000)

4
plat/mediatek/mt8186/include/sspm_reg.h
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@ -9,12 +9,8 @@
#include "platform_def.h"
#define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) /* SSPM view: 0x30040000 */
#define SSPM_CFGREG_ADDR(ofs) (SSPM_CFGREG_BASE + (ofs))
#define SSPM_MCDI_SHARE_SRAM (IO_PHYS + 0x420000)
#define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000)
#define SSPM_HW_SEM SSPM_CFGREG_ADDR(0x0048)
#define SSPM_ACAO_INT_SET SSPM_CFGREG_ADDR(0x00D8)
#define SSPM_ACAO_INT_CLR SSPM_CFGREG_ADDR(0x00DC)