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fix(cpus): workaround for Cortex-X925 erratum 2963999

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Cortex-X925 erratum 2963999 that applies to r0p0 and is fixed in
r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I447fd359ea32e1d274e1245886e1de57d14f082c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2025-02-07 15:17:09 -06:00
parent 5f32fd2145
commit 29bda258d5
3 changed files with 22 additions and 0 deletions
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3
docs/design/cpu-specific-build-macros.rst
View File

@ -897,6 +897,9 @@ For Cortex-X4, the following errata build flags are defined :
For Cortex-X925, the following errata build flags are defined : For Cortex-X925, the following errata build flags are defined :
- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925
CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 - ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open.

15
lib/cpus/aarch64/cortex_x925.S
View File

@ -27,6 +27,21 @@ add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_A
check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999
/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
ldr x0, =0x0
msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
ldr x0, =0xd5380000
msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
ldr x0, =0xFFFFFF40
msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
ldr x0, =0x000080010033f
msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
isb
workaround_reset_end cortex_x925, ERRATUM(2963999)
check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0)
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ /* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46)

4
lib/cpus/cpu-ops.mk
View File

@ -904,6 +904,10 @@ CPU_FLAG_LIST += ERRATA_X4_3076789
# of the Cortex-X4 cpu and is still open. # of the Cortex-X4 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X4_3701758 CPU_FLAG_LIST += ERRATA_X4_3701758
# Flag to apply erratum 2963999 workaround during reset. This erratum applies
# to revisions r0p0 of the Cortex-X925 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_X925_2963999
# Flag to apply erratum 3701747 workaround during context save/restore of # Flag to apply erratum 3701747 workaround during context save/restore of
# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of the # ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 of the
# Cortex-X925 cpu and is still open. # Cortex-X925 cpu and is still open.