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Merge "fix(versal): replace FPD_MAINCCI* macros" into integration

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Joanna Farley 2023-04-17 13:08:26 +02:00 committed by TrustedFirmware Code Review
commit 114495b548
2 changed files with 2 additions and 4 deletions
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2
plat/xilinx/versal/aarch64/versal_common.c
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@ -23,7 +23,7 @@ const mmap_region_t plat_versal_mmap[] = {
MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(FPD_MAINCCI_BASE, FPD_MAINCCI_SIZE, MT_DEVICE | MT_RW |
MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
MT_SECURE),
{ 0 }
};

4
plat/xilinx/versal/include/versal_def.h
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@ -50,6 +50,7 @@
* CCI-400 related constants
******************************************************************************/
#define PLAT_ARM_CCI_BASE 0xFD000000
#define PLAT_ARM_CCI_SIZE 0x00100000
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
@ -110,9 +111,6 @@
#define CRF_RST_APU_ACPU_RESET (1 << 0)
#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
#define FPD_MAINCCI_BASE 0xFD000000
#define FPD_MAINCCI_SIZE 0x00100000
/* APU registers and bitfields */
#define FPD_APU_BASE 0xFD5C0000U
#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)