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feat(ti): disable L2 dataless UniqueClean evictions

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Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e
This commit is contained in:
Andrew Davis 2022-09-01 11:02:59 -05:00
parent 81858a353f
commit 10d5cf1b26
1 changed files with 6 additions and 0 deletions
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6
plat/ti/k3/common/k3_helpers.S
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@ -118,6 +118,12 @@ a72:
orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
msr CORTEX_A72_L2CTLR_EL1, x0 msr CORTEX_A72_L2CTLR_EL1, x0
mrs x0, CORTEX_A72_L2ACTLR_EL1
/* Enable L2 UniqueClean evictions with data */
orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
msr CORTEX_A72_L2ACTLR_EL1, x0
isb isb
ret ret
endfunc plat_reset_handler endfunc plat_reset_handler