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feat(ti): disable L2 dataless UniqueClean evictions
Do this early before we enable caching as a workaround for ARM A72 Errata #854172. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e
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@ -118,6 +118,12 @@ a72:
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orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
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orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
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msr CORTEX_A72_L2CTLR_EL1, x0
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mrs x0, CORTEX_A72_L2ACTLR_EL1
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/* Enable L2 UniqueClean evictions with data */
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orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
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msr CORTEX_A72_L2ACTLR_EL1, x0
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isb
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ret
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endfunc plat_reset_handler
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