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Merge changes I8667f362,Ia0bd832c into integration

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* changes:
  feat(intel): setup FPGA interface for Agilex
  fix(intel): fix pinmux handoff bug on Agilex
This commit is contained in:
Sandrine Bailleux 2022-11-28 15:07:11 +01:00 committed by TrustedFirmware Code Review
commit 086d981657
2 changed files with 44 additions and 9 deletions
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25
plat/intel/soc/agilex/include/agilex_pinmux.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, Intel Corporation. All rights reserved. * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,10 +7,25 @@
#ifndef AGX_PINMUX_H #ifndef AGX_PINMUX_H
#define AGX_PINMUX_H #define AGX_PINMUX_H
#define AGX_PINMUX_PIN0SEL 0xffd13000 #define AGX_PINMUX_BASE 0xffd13000
#define AGX_PINMUX_IO0CTRL 0xffd13130 #define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000)
#define AGX_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 #define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130)
#define AGX_PINMUX_IO0_DELAY 0xffd13400 #define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300)
#define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304)
#define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308)
#define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320)
#define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328)
#define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c)
#define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354)
#define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400)
#define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4)
#define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8)
#define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16)
#define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24)
#define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0)
#define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8)
#define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16)
#include "socfpga_handoff.h" #include "socfpga_handoff.h"

28
plat/intel/soc/agilex/soc/agilex_pinmux.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, Intel Corporation. All rights reserved. * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -188,7 +188,27 @@ const uint32_t sysmgr_pinmux_array_iodelay[] = {
void config_fpgaintf_mod(void) void config_fpgaintf_mod(void)
{ {
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8); uint32_t val;
val = 0;
if (mmio_read_32(AGX_PINMUX_NAND_USEFPGA) & 1)
val |= AGX_PINMUX_NAND_USEFPGA_VAL;
if (mmio_read_32(AGX_PINMUX_SDMMC_USEFPGA) & 1)
val |= AGX_PINMUX_SDMMC_USEFPGA_VAL;
if (mmio_read_32(AGX_PINMUX_SPIM0_USEFPGA) & 1)
val |= AGX_PINMUX_SPIM0_USEFPGA_VAL;
if (mmio_read_32(AGX_PINMUX_SPIM1_USEFPGA) & 1)
val |= AGX_PINMUX_SPIM1_USEFPGA_VAL;
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), val);
val = 0;
if (mmio_read_32(AGX_PINMUX_EMAC0_USEFPGA) & 1)
val |= AGX_PINMUX_EMAC0_USEFPGA_VAL;
if (mmio_read_32(AGX_PINMUX_EMAC1_USEFPGA) & 1)
val |= AGX_PINMUX_EMAC1_USEFPGA_VAL;
if (mmio_read_32(AGX_PINMUX_EMAC2_USEFPGA) & 1)
val |= AGX_PINMUX_EMAC2_USEFPGA_VAL;
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), val);
} }
@ -208,8 +228,8 @@ void config_pinmux(handoff *hoff_ptr)
hoff_ptr->pinmux_io_array[i+1]); hoff_ptr->pinmux_io_array[i+1]);
} }
for (i = 0; i < 42; i += 2) { for (i = 0; i < 40; i += 2) {
mmio_write_32(AGX_PINMUX_PINMUX_EMAC0_USEFPGA + mmio_write_32(AGX_PINMUX_EMAC0_USEFPGA +
hoff_ptr->pinmux_fpga_array[i], hoff_ptr->pinmux_fpga_array[i],
hoff_ptr->pinmux_fpga_array[i+1]); hoff_ptr->pinmux_fpga_array[i+1]);
} }